beand3.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
entity bandgate3 is
port(a: in std_logic_vector(2 downto 0);
      z:  out std_logic
      );
end bandgate3;
Architecture reg of bandgate3 is
begin
   process(a)
   	begin
   		case a is
   			when "000"=> z<='0';
   			when "001"=> z<='0';
   			when "010"=> z<='0';
   			when "011"=> z<='0';
   			when "100"=> z<='0';
   			when "101"=> z<='0';
   			when "110"=> z<='0';
   			when others=> z<='1';
   		end case;	    
   	end process;	
end reg;