dff7474.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
entity dff7474 is
port(D,clk, pr,cr: in std_logic;
	q, nq: out std_logic
	);
end dff7474;
architecture reg of dff7474 is
begin
	process (d,clk,pr,cr)
	   begin
	   if (cr='1' and pr='1') then
	       q<= '0';
	       nq<='1';
	   elsif (clk'event and clk='1') then
	    q<=d;
	    nq<=not d;
	   end if;
	   end process;
end reg;