benor3.vhd

vhdl programs to use as a lab experiment all advance programs

library ieee;
use ieee.std_logic_1164.all;
entity bnorgate3 is
port(a: in std_logic_vector(2 downto 0);
      z:  out std_logic
      );
end bnorgate3;
Architecture reg of bnorgate3 is
begin
   process(a)
   	begin
   		case a is
   			when "000"=> z<='1';
   			when "001"=> z<='0';
   			when "010"=> z<='0';
   			when "011"=> z<='0';
   			when "100"=> z<='0';
   			when "101"=> z<='0';
   			when "110"=> z<='0';
   			when others=> z<='0';
   		end case;	    
   	end process;	
end reg;