4x16demux74154.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity demux74154 is
port(din: in std_logic;
		s: in std_logic_vector(3 downto 0);
		y: out std_logic_vector(15 downto 0)
		);
end demux74154;
architecture reg of demux74154 is
signal sy: std_logic_vector (15 downto 0);
begin
	process(din, s)
	begin
		case s is 
			when "0000" => sy<="000000000000000"&din;
			when "0001" => sy<="00000000000000" &din & '0';
			when "0010" => sy<="0000000000000" & din & "00";
			when "0011" => sy<="000000000000"&din&"000" ;
			when "0100" => sy<="00000000000" & din &"0000";
			when "0101" => sy<="0000000000"& din &"00000";
			when "0110" => sy<="000000000"& din &"000000";
			when "0111" => sy<="00000000" & din &"0000000";
			when "1000" => sy<="0000000"& din &"00000000";
			when "1001" => sy<="000000"& din &"000000000";
			when "1010" => sy<="00000"  & din &"0000000000";
			when "1011" => sy<="0000"& din &"00000000000";
			when "1100" => sy<="000" & din & "000000000000";
			when "1101" => sy<="00"& din &"0000000000000";
			when "1110" => sy<="0"& din &"00000000000000";
			when "1111" => sy<= din &"000000000000000";
			when others => sy<= "UUUUUUUUUUUUUUUU";
			end case;
	end process;
	y<= sy;
end reg;