siva.mpf

vhdl programs to use as a lab experiment all advance programs

[Library]
others = C:\altera\81\modelsim_ae\win32aloem/../modelsim.ini

; Altera specific primitive library mappings 


work = work
[vcom]
; Turn on VHDL-1993 as the default. Normally is off.
; VHDL93 = 1

; Show source line containing error. Default is off.
; Show_source = 1

; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; .ini file has Explict enable so that std_logic_signed/unsigned
; will match synthesis tools behavior.
Explicit = 1

; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = false

; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1

; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1

; Turn off "loading..." messages. Default is messages on.
; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:
;	-- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1

; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.

; RequireConfigForAllDefaultBinding = 1 

VHDL93 = 2002
NoDebug = 0
CheckSynthesis = 0
NoVitalCheck = 0
Optimize_1164 = 1
NoVital = 0
Quiet = 0
Show_source = 0
DisableOpt = 0
VcomZeroIn = 0
CoverageNoSub = 0
NoCoverage = 1
CoverCells = 0
CoverExcludeDefault = 0
CoverOpt = 2
Show_Warning1 = 1
Show_Warning2 = 1
Show_Warning3 = 1
Show_Warning4 = 1
Show_Warning5 = 1
[vlog]

; Turn off inclusion of debugging info within design units. Default is to include.
; NoDebug = 1

; Turn off "loading..." messages. Default is messages on.
; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Turns on incremental compilation of modules 
; Incremental = 1

vlog95compat = 0
Vlog01Compat = 0
Svlog = 0
CoverCells = 0
CoverExcludeDefault = 0
CoverOpt = 2
OptionFile = C:/altera/81/modelsim_ae/examples/vlog.opt
Quiet = 0
Show_source = 0
Protect = 0
NoDebug = 0
Hazard = 0
UpCase = 0
DisableOpt = 0
VlogZeroIn = 0
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 1ps

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
UserTimeUnit = default

; Default run length
RunLength = 100 ps

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Directive to license manager:
; vhdl          Immediately reserve a VHDL license
; vlog          Immediately reserve a Verilog license
; plus          Immediately reserve a VHDL and Verilog license
; nomgc         Do not look for Mentor Graphics Licenses
; nomti         Do not look for Model Technology Licenses
; noqueue       Do not wait in the license queue when a license isn't available
; License = plus

; Stop the simulator after an assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; Assertion Message Format
; %S - Severity Level 
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; Assertion File - alternate file for storing assertion messages
; AssertFile = assert.log

; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic

; VSIM Startup command
; Startup = do startup.do

; File for saving command transcript
TranscriptFile = transcript

; File for saving command history 
;CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described 
; in VHDL or Verilog format. For VHDL, PathSeparator = /
; for Verilog, PathSeparator = .
PathSeparator = /

; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :

; Disable assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1

; Default force kind. May be freeze, drive, or deposit 
; or in other terms, fixed, wired or charged.
; DefaultForceKind = freeze

; If zero, open files when elaborated
; else open files on first read or write
; DelayFileOpen = 0

; Control VHDL files opened for write
;   0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0

; Control number of VHDL files open concurrently
;   This number should always be less then the 
;   current ulimit setting for max file descriptors
;   0 = unlimited
ConcurrentFileLimit = 40

; This controls the number of hierarchical regions displayed as
; part of a signal name shown in the waveform window.  The default
; value or a value of zero tells VSIM to display the full name.
; WaveSignalNameWidth = 0

; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1

; Turn off warnings from the IEEE numeric_std and numeric_bit
; packages.
; NumericStdNoWarnings = 1

; Control the format of a generate statement label. Don't quote it.
; GenerateFormat = %s__%d

; Specify whether checkpoint files should be compressed.
; The default is to be compressed.
; CheckpointCompressMode = 0

; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
VoptFlow = 1
[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 4
Project_File_0 = E:/myhdl/notgate.vhd
Project_File_P_0 = cover_toggle 0 vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_exttoggle 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230214167 cover_fsm 0 cover_branch 0 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 cover_expr 0 vhdl_use93 2002 cover_stmt 0
Project_File_1 = E:/myhdl/benand2.vhd
Project_File_P_1 = cover_toggle 0 vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_exttoggle 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230214918 cover_fsm 0 cover_branch 0 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 cover_expr 0 vhdl_use93 2002 cover_stmt 0
Project_File_2 = E:/myhdl/bexor3.vhd
Project_File_P_2 = cover_toggle 0 vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_exttoggle 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 vhdl_disableopt 0 cover_branch 0 cover_fsm 0 last_compile 1230215933 folder {Top Level} cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 2 vhdl_options {} vhdl_warn5 1 toggle - ood 0 compile_to work compile_order 3 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 2002
Project_File_3 = E:/myhdl/nand3.vhd
Project_File_P_3 = cover_toggle 0 vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_exttoggle 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1230213547 cover_fsm 0 cover_branch 0 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 2 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 cover_expr 0 vhdl_use93 2002 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick = 
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick = 
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick = 
PSL_DoubleClick = Edit
PSL_CustomDoubleClick = 
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick = 
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick = 
TCL_DoubleClick = Edit
TCL_CustomDoubleClick = 
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick = 
VCD_DoubleClick = Edit
VCD_CustomDoubleClick = 
SDF_DoubleClick = Edit
SDF_CustomDoubleClick = 
XML_DoubleClick = Edit
XML_CustomDoubleClick = 
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick = 
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick = 
EditorState = {tabbed horizontal 1} {E:/myhdl/xnor3.vhd 0 0} {E:/myhdl/bexnor3.vhd 0 0}
Project_Major_Version = 6
Project_Minor_Version = 3