xnor2.vhd.bak

vhdl programs to use as a lab experiment all advance programs

library ieee;
use ieee.std_logic_1164.all;
entity xnorgate2 is
port(a,b: in std_logic;
      z:  out std_logic
      );
end xnorgate2;
Architecture reg of xnorgate2 is
begin
   z<= a or b;
end reg;