benor2.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
entity bnorgate2 is
port(a,b: in std_logic;
      z:  out std_logic
      );
end bnorgate2;
Architecture reg of bnorgate2 is
begin
   process(a,b)
   	begin
   		if (a='0'and b='0')then z<= '1';
   		elsif(a='0'and b='1')then z<= '0';
   		elsif(a='1'and b='0')then z<= '0';
   		else z<='0';
   		end if;
   	end process;	
end reg;