or3.vhd

vhdl programs to use as a lab experiment all advance programs

library ieee;
use ieee.std_logic_1164.all;
entity orgate3 is
port(a,b,c: in std_logic;
      z:  out std_logic
      );
end orgate3;
Architecture reg of orgate3 is
begin
   z<= a or b or c;
end reg;