notgate.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
entity notgate is
port(a: in std_logic;
      z:  out std_logic
      );
end notgate;
Architecture reg of notgate is
begin
   z<= not a;
end reg;