4bitcount7493.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity  count7493 is
port(clk,reset: in std_logic;
	count: out unsigned (3 downto 0)
	);
end count7493;
architecture reg of count7493 is
signal co:unsigned (3 downto 0);
begin
	process (clk)
	 begin
	   if  (reset='1') then 
	     co<="0000";
	   elsif (clk'event and clk='1') then
	      co<=co+1;
	   end if;
	 end process;
	count<= co; 
end reg;