autozero.vhd

DC remove example (one from DSP steps)

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

package AutoZero_pkg IS
component AutoZero IS
    --generic (
    --          LPF_A  : integer range 0 to 32767 := 200;   --2xLPF_A+LPF_B=32768
    --          LPF_B  : integer range 0 to 32767 := 32368
    --        );   
        port (
        clk         : in  STD_LOGIC;
        Din         : in  STD_LOGIC_VECTOR(15 downto 0);
        Dien        : in  STD_LOGIC;
        reset       : in  STD_LOGIC;
        Dout        : out std_logic_vector(15 DOWNTO 0);
        Doen        : out std_logic
        );
end component AutoZero;
end package AutoZero_pkg;


library IEEE;
use IEEE.STD_LOGIC_1164.all;    
USE IEEE.numeric_std.ALL;

--library unisim;
--use unisim.VCOMPONENTS.all;


    entity AutoZero is
    --generic (
    --          LPF_A  : integer range 0 to 32767 := 200;   --2xLPF_A+LPF_B=32768
    --          LPF_B  : integer range 0 to 32767 := 32368
    --        );   
            
        port (
        clk         : in  STD_LOGIC;
        Din         : in  STD_LOGIC_VECTOR(15 downto 0);
        Dien        : in  STD_LOGIC;
        reset       : in  STD_LOGIC;
        Dout        : out std_logic_vector(15 DOWNTO 0);
        Doen        : out std_logic
        );
    end AutoZero;


architecture ARCH_behav of AutoZero is

attribute period : string;
attribute period of clk : signal is "290 MHz";

    -- diagram signals declarations
    signal Din_s            : signed(15 downto 0);
    signal Dout_r           : signed(16 downto 0) := (OTHERS => '0');
--    signal integr_r         : std_logic_vector(47 downto 0);
    signal integr_s         : signed(31 downto 0) := (OTHERS => '0');
    signal offset_s         : signed(9 downto 0);
    signal st1              : std_logic;
    
    
begin
--!!!!!!!!!!!!!!!!!!!!!
  Din_s    <= signed(Din);
  offset_s <= signed(integr_s(29 downto 20)); 
  Dout     <= std_logic_vector(Dout_r(15 downto 0));
  Doen     <= Dien;
--  integr_s <= signed(integr_r);
--!!!!!!!!!!!!!!!!!!   


  dien_proc : PROCESS (clk)
  BEGIN
    if clk'event AND clk = '1' THEN
      if reset = '1' then
         integr_s <= (OTHERS => '0');
         st1 <= '0';
      else   
         st1 <= Dien;
         if Dien = '1' THEN
            Dout_r <= resize(Din_s, 17) - resize(offset_s, 17);
            integr_s <= integr_s + Dout_r;
         end if;  
         if st1 = '1' then
            if Dout_r(16) /= Dout_r(15) then
                Dout_r(15) <= Dout_r(16);
                Dout_r(14 downto 1) <= (OTHERS => NOT Dout_r(16));
                Dout_r(0) <= '1';
            end if;
            if integr_s(30) /= integr_s(29) then
                integr_s(29) <= integr_s(30);
                integr_s(28 downto 1) <= (OTHERS => NOT integr_s(30));
                integr_s(0) <= '1';
            end if;
         end if; --st1   
      end if; --reset   
    end if; --clk  
  end process dien_proc;
    
end ARCH_behav;