div4limit.v

来自「基于VHDL语言的一个FFT快速傅里叶变换程序。采用4蝶形算法」· Verilog 代码 · 共 69 行

/*
 * filename: div4limit.v
 *
 * version: 2007-04-21
 *
 * funciton: 将乘法器的输出做精度截取.当invert=1时,这里的截取已经包含了
 *     除以4的运算,这样3次循环后,就相当于除以256.
 *
 */

module	div4limit
(
	clk8x,
	data_in,
	data_out,
	invert,
	overflow
);

parameter				WIDTH = 16;

input					clk8x;
input	[2*WIDTH:0]		data_in;
input					invert;

output	[WIDTH-1:0]		data_out;
output					overflow;

reg		[WIDTH-1:0]		data_out;	
reg						overflow;

always @ (posedge clk8x)
begin
	if (invert)
	begin
		if	(data_in[2*WIDTH : 2*WIDTH-3]==4'b1111 || data_in[2*WIDTH : 2*WIDTH-3]==4'b0000)
		begin
			overflow <= 1'b0;
			data_out <= data_in[2*WIDTH-3 : WIDTH-2];
		end
		else
		begin
			overflow <= 1'b1;
			if (data_in[2*WIDTH])
				data_out <= 16'hffff;
			else
				data_out <= 16'b0;
		end
	end
	else
	begin
		if	(data_in[2*WIDTH : 2*WIDTH-5]==6'b111111 || data_in[2*WIDTH : 2*WIDTH-5]==6'b000000)
		begin
			overflow <= 1'b0;
			data_out <= data_in[2*WIDTH-5 : WIDTH-4];
		end
		else
		begin
			overflow <= 1'b1;
			if (data_in[2*WIDTH])
				data_out <= 16'hffff;
			else
				data_out <= 16'b0;
		end
	end
end

endmodule