fifo2.map.rpt

一个关于FIFO的VERILOG程序。很不错的。

+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; fifo2.v                          ; yes             ; User Verilog HDL File  ; F:/qutus/fifo_2/fifo2.v      ;
+----------------------------------+-----------------+------------------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 86    ;
; Total combinational functions               ; 48    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 42    ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 4     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 48    ;
;     -- arithmetic mode                      ; 0     ;
; Total registers                             ; 86    ;
; I/O pins                                    ; 38    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 86    ;
; Total fan-out                               ; 471   ;
; Average fan-out                             ; 2.74  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |fifo2                     ; 48 (48)           ; 86 (86)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 38   ; 0            ; |fifo2              ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 86    ;
; Number of registers using Synchronous Clear  ; 19    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 80    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |fifo2|dout[0]~reg0        ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |fifo2|count[1]            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |fifo2 ;
+----------------+-------+----------------------------------------------+
; Parameter Name ; Value ; Type                                         ;
+----------------+-------+----------------------------------------------+
; depth          ; 2     ; Integer                                      ;
; max_count      ; 11    ; Binary                                       ;
+----------------+-------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 21 11:12:52 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo2 -c fifo2
Info: Found 1 design units, including 1 entities, in source file fifo2.v
    Info: Found entity 1: fifo2
Info: Elaborating entity "fifo2" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at fifo2.v(55): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at fifo2.v(71): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at fifo2.v(90): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at fifo2.v(93): truncated value with size 32 to match size of target (2)
Info: Duplicate registers merged to single register
    Info: Duplicate register "tail[0]" merged to single register "fifomem~4"
    Info: Duplicate register "tail[1]" merged to single register "fifomem~5"
Info: Implemented 150 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 18 output pins
    Info: Implemented 112 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue Apr 21 11:12:53 2009
    Info: Elapsed time: 00:00:01


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in F:/qutus/fifo_2/fifo2.map.smsg.