fifo2.tan.qmsg

一个关于FIFO的VERILOG程序。很不错的。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[1\] register fifomem~22 250.88 MHz 3.986 ns Internal " "Info: Clock \"clk\" has Internal fmax of 250.88 MHz between source register \"count\[1\]\" and destination register \"fifomem~22\" (period= 3.986 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.723 ns + Longest register register " "Info: + Longest register to register delay is 3.723 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LCFF_X24_Y10_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y10_N9; Fanout = 7; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count[1] } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.370 ns) 0.832 ns always2~23 2 COMB LCCOMB_X24_Y10_N14 5 " "Info: 2: + IC(0.462 ns) + CELL(0.370 ns) = 0.832 ns; Loc. = LCCOMB_X24_Y10_N14; Fanout = 5; COMB Node = 'always2~23'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.832 ns" { count[1] always2~23 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.615 ns) 1.847 ns rtl~97 3 COMB LCCOMB_X24_Y10_N0 16 " "Info: 3: + IC(0.400 ns) + CELL(0.615 ns) = 1.847 ns; Loc. = LCCOMB_X24_Y10_N0; Fanout = 16; COMB Node = 'rtl~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.015 ns" { always2~23 rtl~97 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.855 ns) 3.723 ns fifomem~22 4 REG LCFF_X25_Y10_N15 1 " "Info: 4: + IC(1.021 ns) + CELL(0.855 ns) = 3.723 ns; Loc. = LCFF_X25_Y10_N15; Fanout = 1; REG Node = 'fifomem~22'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.876 ns" { rtl~97 fifomem~22 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.840 ns ( 49.42 % ) " "Info: Total cell delay = 1.840 ns ( 49.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.883 ns ( 50.58 % ) " "Info: Total interconnect delay = 1.883 ns ( 50.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.723 ns" { count[1] always2~23 rtl~97 fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.723 ns" { count[1] always2~23 rtl~97 fifomem~22 } { 0.000ns 0.462ns 0.400ns 1.021ns } { 0.000ns 0.370ns 0.615ns 0.855ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.816 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 86 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 86; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.816 ns fifomem~22 3 REG LCFF_X25_Y10_N15 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X25_Y10_N15; Fanout = 1; REG Node = 'fifomem~22'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk~clkctrl fifomem~22 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.13 % ) " "Info: Total cell delay = 1.806 ns ( 64.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 35.87 % ) " "Info: Total interconnect delay = 1.010 ns ( 35.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl fifomem~22 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.815 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 86 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 86; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.870 ns) + CELL(0.666 ns) 2.815 ns count\[1\] 3 REG LCFF_X24_Y10_N9 7 " "Info: 3: + IC(0.870 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X24_Y10_N9; Fanout = 7; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.536 ns" { clk~clkctrl count[1] } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.16 % ) " "Info: Total cell delay = 1.806 ns ( 64.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 35.84 % ) " "Info: Total interconnect delay = 1.009 ns ( 35.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl count[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl count[1] } { 0.000ns 0.000ns 0.139ns 0.870ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl fifomem~22 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl count[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl count[1] } { 0.000ns 0.000ns 0.139ns 0.870ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 98 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.723 ns" { count[1] always2~23 rtl~97 fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.723 ns" { count[1] always2~23 rtl~97 fifomem~22 } { 0.000ns 0.462ns 0.400ns 1.021ns } { 0.000ns 0.370ns 0.615ns 0.855ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl fifomem~22 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl count[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl count[1] } { 0.000ns 0.000ns 0.139ns 0.870ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "fifomem~22 writep clk 8.259 ns register " "Info: tsu for register \"fifomem~22\" (data pin = \"writep\", clock pin = \"clk\") is 8.259 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.115 ns + Longest pin register " "Info: + Longest pin to register delay is 11.115 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns writep 1 PIN PIN_82 4 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_82; Fanout = 4; PIN Node = 'writep'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { writep } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.626 ns) + CELL(0.624 ns) 8.224 ns always2~23 2 COMB LCCOMB_X24_Y10_N14 5 " "Info: 2: + IC(6.626 ns) + CELL(0.624 ns) = 8.224 ns; Loc. = LCCOMB_X24_Y10_N14; Fanout = 5; COMB Node = 'always2~23'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.250 ns" { writep always2~23 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.615 ns) 9.239 ns rtl~97 3 COMB LCCOMB_X24_Y10_N0 16 " "Info: 3: + IC(0.400 ns) + CELL(0.615 ns) = 9.239 ns; Loc. = LCCOMB_X24_Y10_N0; Fanout = 16; COMB Node = 'rtl~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.015 ns" { always2~23 rtl~97 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.855 ns) 11.115 ns fifomem~22 4 REG LCFF_X25_Y10_N15 1 " "Info: 4: + IC(1.021 ns) + CELL(0.855 ns) = 11.115 ns; Loc. = LCFF_X25_Y10_N15; Fanout = 1; REG Node = 'fifomem~22'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.876 ns" { rtl~97 fifomem~22 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.068 ns ( 27.60 % ) " "Info: Total cell delay = 3.068 ns ( 27.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.047 ns ( 72.40 % ) " "Info: Total interconnect delay = 8.047 ns ( 72.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.115 ns" { writep always2~23 rtl~97 fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.115 ns" { writep writep~combout always2~23 rtl~97 fifomem~22 } { 0.000ns 0.000ns 6.626ns 0.400ns 1.021ns } { 0.000ns 0.974ns 0.624ns 0.615ns 0.855ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.816 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 86 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 86; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.816 ns fifomem~22 3 REG LCFF_X25_Y10_N15 1 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.816 ns; Loc. = LCFF_X25_Y10_N15; Fanout = 1; REG Node = 'fifomem~22'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk~clkctrl fifomem~22 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.13 % ) " "Info: Total cell delay = 1.806 ns ( 64.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 35.87 % ) " "Info: Total interconnect delay = 1.010 ns ( 35.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl fifomem~22 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.115 ns" { writep always2~23 rtl~97 fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.115 ns" { writep writep~combout always2~23 rtl~97 fifomem~22 } { 0.000ns 0.000ns 6.626ns 0.400ns 1.021ns } { 0.000ns 0.974ns 0.624ns 0.615ns 0.855ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.816 ns" { clk clk~clkctrl fifomem~22 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.816 ns" { clk clk~combout clk~clkctrl fifomem~22 } { 0.000ns 0.000ns 0.139ns 0.871ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fullp count\[1\] 10.372 ns register " "Info: tco from clock \"clk\" to destination pin \"fullp\" through register \"count\[1\]\" is 10.372 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.815 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 86 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 86; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.870 ns) + CELL(0.666 ns) 2.815 ns count\[1\] 3 REG LCFF_X24_Y10_N9 7 " "Info: 3: + IC(0.870 ns) + CELL(0.666 ns) = 2.815 ns; Loc. = LCFF_X24_Y10_N9; Fanout = 7; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.536 ns" { clk~clkctrl count[1] } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.16 % ) " "Info: Total cell delay = 1.806 ns ( 64.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 35.84 % ) " "Info: Total interconnect delay = 1.009 ns ( 35.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl count[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl count[1] } { 0.000ns 0.000ns 0.139ns 0.870ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 98 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.253 ns + Longest register pin " "Info: + Longest register to pin delay is 7.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LCFF_X24_Y10_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y10_N9; Fanout = 7; REG Node = 'count\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count[1] } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.156 ns) + CELL(0.370 ns) 1.526 ns Equal1~13 2 COMB LCCOMB_X23_Y10_N18 1 " "Info: 2: + IC(1.156 ns) + CELL(0.370 ns) = 1.526 ns; Loc. = LCCOMB_X23_Y10_N18; Fanout = 1; COMB Node = 'Equal1~13'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.526 ns" { count[1] Equal1~13 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.471 ns) + CELL(3.256 ns) 7.253 ns fullp 3 PIN PIN_94 0 " "Info: 3: + IC(2.471 ns) + CELL(3.256 ns) = 7.253 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'fullp'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.727 ns" { Equal1~13 fullp } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.626 ns ( 49.99 % ) " "Info: Total cell delay = 3.626 ns ( 49.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.627 ns ( 50.01 % ) " "Info: Total interconnect delay = 3.627 ns ( 50.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.253 ns" { count[1] Equal1~13 fullp } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.253 ns" { count[1] Equal1~13 fullp } { 0.000ns 1.156ns 2.471ns } { 0.000ns 0.370ns 3.256ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.815 ns" { clk clk~clkctrl count[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.815 ns" { clk clk~combout clk~clkctrl count[1] } { 0.000ns 0.000ns 0.139ns 0.870ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.253 ns" { count[1] Equal1~13 fullp } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.253 ns" { count[1] Equal1~13 fullp } { 0.000ns 1.156ns 2.471ns } { 0.000ns 0.370ns 3.256ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "fifomem~108 din\[11\] clk 0.241 ns register " "Info: th for register \"fifomem~108\" (data pin = \"din\[11\]\", clock pin = \"clk\") is 0.241 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.833 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.833 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 86 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 86; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.888 ns) + CELL(0.666 ns) 2.833 ns fifomem~108 3 REG LCFF_X23_Y11_N13 1 " "Info: 3: + IC(0.888 ns) + CELL(0.666 ns) = 2.833 ns; Loc. = LCFF_X23_Y11_N13; Fanout = 1; REG Node = 'fifomem~108'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.554 ns" { clk~clkctrl fifomem~108 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.75 % ) " "Info: Total cell delay = 1.806 ns ( 63.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.027 ns ( 36.25 % ) " "Info: Total interconnect delay = 1.027 ns ( 36.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.833 ns" { clk clk~clkctrl fifomem~108 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.833 ns" { clk clk~combout clk~clkctrl fifomem~108 } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.898 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.898 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns din\[11\] 1 PIN PIN_131 4 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_131; Fanout = 4; PIN Node = 'din\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { din[11] } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.434 ns) + CELL(0.206 ns) 2.790 ns fifomem~108feeder 2 COMB LCCOMB_X23_Y11_N12 1 " "Info: 2: + IC(1.434 ns) + CELL(0.206 ns) = 2.790 ns; Loc. = LCCOMB_X23_Y11_N12; Fanout = 1; COMB Node = 'fifomem~108feeder'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.640 ns" { din[11] fifomem~108feeder } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.898 ns fifomem~108 3 REG LCFF_X23_Y11_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 2.898 ns; Loc. = LCFF_X23_Y11_N13; Fanout = 1; REG Node = 'fifomem~108'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { fifomem~108feeder fifomem~108 } "NODE_NAME" } } { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.464 ns ( 50.52 % ) " "Info: Total cell delay = 1.464 ns ( 50.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.434 ns ( 49.48 % ) " "Info: Total interconnect delay = 1.434 ns ( 49.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.898 ns" { din[11] fifomem~108feeder fifomem~108 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.898 ns" { din[11] din[11]~combout fifomem~108feeder fifomem~108 } { 0.000ns 0.000ns 1.434ns 0.000ns } { 0.000ns 1.150ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.833 ns" { clk clk~clkctrl fifomem~108 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.833 ns" { clk clk~combout clk~clkctrl fifomem~108 } { 0.000ns 0.000ns 0.139ns 0.888ns } { 0.000ns 1.140ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.898 ns" { din[11] fifomem~108feeder fifomem~108 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.898 ns" { din[11] din[11]~combout fifomem~108feeder fifomem~108 } { 0.000ns 0.000ns 1.434ns 0.000ns } { 0.000ns 1.150ns 0.206ns 0.108ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}