fifo2.map.qmsg

一个关于FIFO的VERILOG程序。很不错的。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 21 11:12:52 2009 " "Info: Processing started: Tue Apr 21 11:12:52 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fifo2 -c fifo2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fifo2 -c fifo2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "fifo2.v(45) " "Warning (10268): Verilog HDL information at fifo2.v(45): Always Construct contains both blocking and non-blocking assignments" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 45 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fifo2.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo2 " "Info: Found entity 1: fifo2" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fifo2 " "Info: Elaborating entity \"fifo2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 fifo2.v(55) " "Warning (10230): Verilog HDL assignment warning at fifo2.v(55): truncated value with size 32 to match size of target (2)" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 fifo2.v(71) " "Warning (10230): Verilog HDL assignment warning at fifo2.v(71): truncated value with size 32 to match size of target (2)" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 fifo2.v(90) " "Warning (10230): Verilog HDL assignment warning at fifo2.v(90): truncated value with size 32 to match size of target (2)" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 fifo2.v(93) " "Warning (10230): Verilog HDL assignment warning at fifo2.v(93): truncated value with size 32 to match size of target (2)" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "tail\[0\] fifomem~4 " "Info: Duplicate register \"tail\[0\]\" merged to single register \"fifomem~4\"" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 74 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "tail\[1\] fifomem~5 " "Info: Duplicate register \"tail\[1\]\" merged to single register \"fifomem~5\"" {  } { { "fifo2.v" "" { Text "F:/qutus/fifo_2/fifo2.v" 74 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "150 " "Info: Implemented 150 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "20 " "Info: Implemented 20 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "112 " "Info: Implemented 112 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 21 11:12:53 2009 " "Info: Processing ended: Tue Apr 21 11:12:53 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/qutus/fifo_2/fifo2.map.smsg " "Info: Generated suppressed messages file F:/qutus/fifo_2/fifo2.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}