jk_ff.tan.qmsg

来自「这是我自己写的一个关于JK触发器的VERILOG 程序。」· QMSG 代码 · 共 9 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 30 21:41:55 2009 " "Info: Processing started: Mon Mar 30 21:41:55 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off jk_ff -c jk_ff --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jk_ff -c jk_ff --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "Mux0~35 " "Warning: Node \"Mux0~35\" is a latch" {  } { { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "j " "Info: Assuming node \"j\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 2 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "k " "Info: Assuming node \"k\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 2 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux0~34 " "Info: Detected gated clock \"Mux0~34\" as buffer" {  } { { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 7 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~34" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "k q Mux0~35 9.633 ns register " "Info: tco from clock \"k\" to destination pin \"q\" through register \"Mux0~35\" is 9.633 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "k source 2.784 ns + Longest register " "Info: + Longest clock path from clock \"k\" to source register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns k 1 CLK PIN_130 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_130; Fanout = 1; CLK Node = 'k'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { k } "NODE_NAME" } } { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.505 ns) 2.222 ns Mux0~34 2 COMB LCCOMB_X33_Y10_N18 1 " "Info: 2: + IC(0.567 ns) + CELL(0.505 ns) = 2.222 ns; Loc. = LCCOMB_X33_Y10_N18; Fanout = 1; COMB Node = 'Mux0~34'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.072 ns" { k Mux0~34 } "NODE_NAME" } } { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.356 ns) + CELL(0.206 ns) 2.784 ns Mux0~35 3 REG LCCOMB_X33_Y10_N12 1 " "Info: 3: + IC(0.356 ns) + CELL(0.206 ns) = 2.784 ns; Loc. = LCCOMB_X33_Y10_N12; Fanout = 1; REG Node = 'Mux0~35'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.562 ns" { Mux0~34 Mux0~35 } "NODE_NAME" } } { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.861 ns ( 66.85 % ) " "Info: Total cell delay = 1.861 ns ( 66.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.923 ns ( 33.15 % ) " "Info: Total interconnect delay = 0.923 ns ( 33.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { k Mux0~34 Mux0~35 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { k k~combout Mux0~34 Mux0~35 } { 0.000ns 0.000ns 0.567ns 0.356ns } { 0.000ns 1.150ns 0.505ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.849 ns + Longest register pin " "Info: + Longest register to pin delay is 6.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Mux0~35 1 REG LCCOMB_X33_Y10_N12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X33_Y10_N12; Fanout = 1; REG Node = 'Mux0~35'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Mux0~35 } "NODE_NAME" } } { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.583 ns) + CELL(3.266 ns) 6.849 ns q 2 PIN PIN_77 0 " "Info: 2: + IC(3.583 ns) + CELL(3.266 ns) = 6.849 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'q'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.849 ns" { Mux0~35 q } "NODE_NAME" } } { "jk_ff.v" "" { Text "F:/qutus/jk_ff/jk_ff.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 47.69 % ) " "Info: Total cell delay = 3.266 ns ( 47.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.583 ns ( 52.31 % ) " "Info: Total interconnect delay = 3.583 ns ( 52.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.849 ns" { Mux0~35 q } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.849 ns" { Mux0~35 q } { 0.000ns 3.583ns } { 0.000ns 3.266ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { k Mux0~34 Mux0~35 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { k k~combout Mux0~34 Mux0~35 } { 0.000ns 0.000ns 0.567ns 0.356ns } { 0.000ns 1.150ns 0.505ns 0.206ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.849 ns" { Mux0~35 q } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.849 ns" { Mux0~35 q } { 0.000ns 3.583ns } { 0.000ns 3.266ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 30 21:41:56 2009 " "Info: Processing ended: Mon Mar 30 21:41:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}