jk.map.qmsg

这是我自己写的一个关于JK触发器的VERILOG 程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 08 22:53:14 2009 " "Info: Processing started: Wed Apr 08 22:53:14 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jk -c jk " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jk -c jk" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jk.v" { { "Info" "ISGN_ENTITY_NAME" "1 jk " "Info: Found entity 1: jk" {  } { { "jk.v" "" { Text "F:/qutus/jk_ff/jk/jk.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jk_0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jk_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 jk_0 " "Info: Found entity 1: jk_0" {  } { { "jk_0.v" "" { Text "F:/qutus/jk_ff/jk/jk_0.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "a jk.v(14) " "Error (10137): Verilog HDL Procedural Assignment error at jk.v(14): object \"a\" on left-hand side of assignment must have a variable data type" {  } { { "jk.v" "" { Text "F:/qutus/jk_ff/jk/jk.v" 14 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Apr 08 22:53:14 2009 " "Error: Processing ended: Wed Apr 08 22:53:14 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}