jk_ff.fit.summary

这是我自己写的一个关于JK触发器的VERILOG 程序。

Fitter Status : Successful - Mon Mar 30 21:41:45 2009
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : jk_ff
Top-level Entity Name : jk_ff
Family : Cyclone II
Device : EP2C8Q208C8
Timing Models : Final
Total logic elements : 2 / 8,256 ( < 1 % )
    Total combinational functions : 2 / 8,256 ( < 1 % )
    Dedicated logic registers : 0 / 8,256 ( 0 % )
Total registers : 0
Total pins : 6 / 138 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )