jk_ff.tan.rpt

这是我自己写的一个关于JK触发器的VERILOG 程序。

Classic Timing Analyzer report for jk_ff
Mon Mar 30 21:41:55 2009
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tco
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                  ;
+------------------------------+-------+---------------+-------------+---------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From    ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+---------+----+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 9.633 ns    ; Mux0~35 ; q  ; k          ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;         ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+---------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; j               ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; k               ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 9.633 ns   ; Mux0~35 ; q  ; k          ;
; N/A   ; None         ; 9.232 ns   ; Mux0~35 ; q  ; j          ;
+-------+--------------+------------+---------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Mon Mar 30 21:41:55 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jk_ff -c jk_ff --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "Mux0~35" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "j" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "k" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux0~34" as buffer
Info: tco from clock "k" to destination pin "q" through register "Mux0~35" is 9.633 ns
    Info: + Longest clock path from clock "k" to source register is 2.784 ns
        Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_130; Fanout = 1; CLK Node = 'k'
        Info: 2: + IC(0.567 ns) + CELL(0.505 ns) = 2.222 ns; Loc. = LCCOMB_X33_Y10_N18; Fanout = 1; COMB Node = 'Mux0~34'
        Info: 3: + IC(0.356 ns) + CELL(0.206 ns) = 2.784 ns; Loc. = LCCOMB_X33_Y10_N12; Fanout = 1; REG Node = 'Mux0~35'
        Info: Total cell delay = 1.861 ns ( 66.85 % )
        Info: Total interconnect delay = 0.923 ns ( 33.15 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 6.849 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X33_Y10_N12; Fanout = 1; REG Node = 'Mux0~35'
        Info: 2: + IC(3.583 ns) + CELL(3.266 ns) = 6.849 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 3.266 ns ( 47.69 % )
        Info: Total interconnect delay = 3.583 ns ( 52.31 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Mon Mar 30 21:41:56 2009
    Info: Elapsed time: 00:00:01