📄 diceng.rpt
字号:
- 3 - A 23 DFFE 2 1 1 0 |shuzi:28|:551
- 4 - A 16 DFFE 2 1 1 0 |shuzi:28|:552
- 8 - B 22 OR2 0 2 0 3 |shuzi:29|lpm_add_sub:553|addcore:adder|pcarry1
- 6 - B 13 OR2 0 2 0 3 |shuzi:29|lpm_add_sub:553|addcore:adder|pcarry2
- 4 - B 15 AND2 0 2 0 1 |shuzi:29|lpm_add_sub:554|addcore:adder|:55
- 3 - B 18 OR2 0 3 0 1 |shuzi:29|lpm_add_sub:555|addcore:adder|pcarry2
- 5 - B 22 AND2 0 2 0 1 |shuzi:29|lpm_add_sub:556|addcore:adder|:55
- 6 - C 05 OR2 ! 1 1 0 14 |shuzi:29|:31
- 4 - B 19 AND2 s 0 2 0 3 |shuzi:29|~32~1
- 1 - A 18 AND2 1 1 0 6 |shuzi:29|:32
- 3 - B 20 OR2 0 2 0 1 |shuzi:29|:44
- 3 - B 15 OR2 ! 0 4 0 6 |shuzi:29|:61
- 2 - B 15 OR2 0 4 0 1 |shuzi:29|:79
- 1 - B 18 OR2 s ! 0 4 0 3 |shuzi:29|~103~1
- 5 - B 20 OR2 ! 0 3 0 5 |shuzi:29|:103
- 3 - B 13 OR2 0 4 0 2 |shuzi:29|:136
- 7 - B 22 OR2 0 3 0 2 |shuzi:29|:138
- 7 - B 13 OR2 0 4 0 2 |shuzi:29|:150
- 4 - B 13 DFFE 2 3 0 2 |shuzi:29|count_h3 (|shuzi:29|:161)
- 5 - A 23 DFFE 2 1 0 3 |shuzi:29|count_h2 (|shuzi:29|:162)
- 3 - B 22 DFFE 2 3 0 4 |shuzi:29|count_h1 (|shuzi:29|:163)
- 6 - B 22 DFFE 2 3 0 4 |shuzi:29|count_h0 (|shuzi:29|:164)
- 1 - B 13 OR2 0 4 0 4 |shuzi:29|:192
- 8 - B 15 OR2 0 4 0 1 |shuzi:29|:202
- 5 - B 15 OR2 0 4 0 1 |shuzi:29|:203
- 6 - B 15 OR2 0 3 0 1 |shuzi:29|:204
- 2 - B 20 OR2 0 4 0 4 |shuzi:29|:223
- 1 - B 15 OR2 0 4 0 5 |shuzi:29|:224
- 7 - B 15 OR2 0 4 0 4 |shuzi:29|:225
- 5 - B 19 OR2 0 4 0 5 |shuzi:29|:226
- 7 - B 20 OR2 0 4 0 2 |shuzi:29|:247
- 5 - B 18 AND2 s 0 2 0 2 |shuzi:29|~252~1
- 7 - B 18 OR2 0 4 0 2 |shuzi:29|:252
- 6 - B 18 OR2 0 4 0 2 |shuzi:29|:262
- 6 - B 20 OR2 0 4 0 2 |shuzi:29|:263
- 8 - B 20 DFFE 2 3 0 4 |shuzi:29|count_l3 (|shuzi:29|:272)
- 8 - B 18 DFFE 2 3 0 5 |shuzi:29|count_l2 (|shuzi:29|:273)
- 8 - C 10 DFFE 2 1 0 6 |shuzi:29|count_l1 (|shuzi:29|:274)
- 1 - B 16 DFFE 2 1 0 6 |shuzi:29|count_l0 (|shuzi:29|:275)
- 8 - B 13 OR2 0 4 0 6 |shuzi:29|:298
- 2 - B 13 OR2 0 4 0 3 |shuzi:29|:299
- 2 - B 22 OR2 0 3 0 4 |shuzi:29|:300
- 4 - B 22 OR2 0 3 0 4 |shuzi:29|:301
- 5 - B 13 DFFE 2 3 1 0 |shuzi:29|:545
- 7 - A 23 DFFE 2 1 1 0 |shuzi:29|:546
- 1 - B 22 DFFE 2 3 1 0 |shuzi:29|:547
- 1 - B 20 DFFE 2 3 1 0 |shuzi:29|:548
- 4 - B 20 DFFE 2 3 1 0 |shuzi:29|:549
- 2 - B 18 DFFE 2 3 1 0 |shuzi:29|:550
- 4 - B 18 DFFE 2 1 1 0 |shuzi:29|:551
- 8 - B 16 DFFE 2 1 1 0 |shuzi:29|:552
- 2 - C 12 OR2 0 2 0 3 |shuzi:30|lpm_add_sub:553|addcore:adder|pcarry1
- 2 - C 16 OR2 0 2 0 3 |shuzi:30|lpm_add_sub:553|addcore:adder|pcarry2
- 1 - C 09 AND2 0 2 0 1 |shuzi:30|lpm_add_sub:554|addcore:adder|:55
- 7 - C 11 OR2 0 3 0 1 |shuzi:30|lpm_add_sub:555|addcore:adder|pcarry2
- 5 - C 12 AND2 0 2 0 1 |shuzi:30|lpm_add_sub:556|addcore:adder|:55
- 1 - C 05 OR2 ! 1 1 0 14 |shuzi:30|:31
- 1 - C 02 AND2 s 0 2 0 3 |shuzi:30|~32~1
- 8 - A 18 AND2 1 1 0 6 |shuzi:30|:32
- 3 - C 11 OR2 0 2 0 1 |shuzi:30|:44
- 3 - C 02 OR2 ! 0 4 0 6 |shuzi:30|:61
- 4 - C 09 OR2 0 4 0 1 |shuzi:30|:79
- 6 - C 11 OR2 s ! 0 4 0 3 |shuzi:30|~103~1
- 8 - C 11 OR2 ! 0 3 0 5 |shuzi:30|:103
- 6 - C 16 OR2 0 4 0 2 |shuzi:30|:136
- 8 - C 12 OR2 0 3 0 2 |shuzi:30|:138
- 4 - C 16 OR2 0 4 0 2 |shuzi:30|:150
- 8 - C 16 DFFE 2 3 0 2 |shuzi:30|count_h3 (|shuzi:30|:161)
- 7 - C 16 DFFE 2 1 0 3 |shuzi:30|count_h2 (|shuzi:30|:162)
- 6 - C 12 DFFE 2 3 0 4 |shuzi:30|count_h1 (|shuzi:30|:163)
- 1 - C 12 DFFE 2 3 0 4 |shuzi:30|count_h0 (|shuzi:30|:164)
- 5 - C 16 OR2 0 4 0 4 |shuzi:30|:192
- 6 - C 09 OR2 0 4 0 1 |shuzi:30|:202
- 4 - C 02 OR2 0 4 0 1 |shuzi:30|:203
- 5 - C 02 OR2 0 3 0 1 |shuzi:30|:204
- 5 - C 09 OR2 0 4 0 4 |shuzi:30|:223
- 2 - C 02 OR2 0 4 0 5 |shuzi:30|:224
- 8 - C 02 OR2 0 4 0 4 |shuzi:30|:225
- 6 - C 02 OR2 0 4 0 5 |shuzi:30|:226
- 1 - C 11 OR2 0 4 0 2 |shuzi:30|:247
- 2 - C 11 AND2 s 0 2 0 2 |shuzi:30|~252~1
- 5 - C 11 OR2 0 4 0 2 |shuzi:30|:252
- 5 - C 05 OR2 0 4 0 2 |shuzi:30|:262
- 4 - C 11 OR2 0 4 0 2 |shuzi:30|:263
- 2 - C 09 DFFE 2 3 0 4 |shuzi:30|count_l3 (|shuzi:30|:272)
- 2 - C 07 DFFE 2 3 0 5 |shuzi:30|count_l2 (|shuzi:30|:273)
- 8 - C 05 DFFE 2 1 0 6 |shuzi:30|count_l1 (|shuzi:30|:274)
- 3 - C 09 DFFE 2 1 0 6 |shuzi:30|count_l0 (|shuzi:30|:275)
- 3 - C 16 OR2 0 4 0 6 |shuzi:30|:298
- 3 - C 12 OR2 0 4 0 3 |shuzi:30|:299
- 7 - C 12 OR2 0 3 0 4 |shuzi:30|:300
- 7 - C 02 OR2 0 3 0 4 |shuzi:30|:301
- 1 - C 16 DFFE 2 3 1 0 |shuzi:30|:545
- 2 - C 13 DFFE 2 1 1 0 |shuzi:30|:546
- 4 - C 12 DFFE 2 3 1 0 |shuzi:30|:547
- 4 - C 10 DFFE 2 3 1 0 |shuzi:30|:548
- 8 - C 09 DFFE 2 3 1 0 |shuzi:30|:549
- 1 - C 07 DFFE 2 3 1 0 |shuzi:30|:550
- 3 - C 05 DFFE 2 1 1 0 |shuzi:30|:551
- 7 - C 09 DFFE 2 1 1 0 |shuzi:30|:552
- 2 - B 05 OR2 0 2 0 3 |shuzi:31|lpm_add_sub:553|addcore:adder|pcarry1
- 1 - B 01 OR2 0 2 0 3 |shuzi:31|lpm_add_sub:553|addcore:adder|pcarry2
- 6 - B 10 AND2 0 2 0 1 |shuzi:31|lpm_add_sub:554|addcore:adder|:55
- 5 - B 11 OR2 0 3 0 1 |shuzi:31|lpm_add_sub:555|addcore:adder|pcarry2
- 6 - B 01 AND2 0 2 0 1 |shuzi:31|lpm_add_sub:556|addcore:adder|:55
- 4 - C 05 OR2 ! 1 1 0 14 |shuzi:31|:31
- 1 - B 07 AND2 s 0 2 0 3 |shuzi:31|~32~1
- 6 - A 18 AND2 1 1 0 6 |shuzi:31|:32
- 2 - B 03 OR2 0 2 0 1 |shuzi:31|:44
- 8 - B 10 OR2 ! 0 4 0 6 |shuzi:31|:61
- 2 - B 10 OR2 0 4 0 1 |shuzi:31|:79
- 3 - B 11 OR2 s ! 0 4 0 3 |shuzi:31|~103~1
- 4 - B 03 OR2 ! 0 3 0 5 |shuzi:31|:103
- 2 - B 01 OR2 0 4 0 2 |shuzi:31|:136
- 7 - B 05 OR2 0 3 0 2 |shuzi:31|:138
- 8 - B 01 OR2 0 4 0 2 |shuzi:31|:150
- 4 - B 07 DFFE 2 3 0 2 |shuzi:31|count_h3 (|shuzi:31|:161)
- 7 - B 01 DFFE 2 1 0 3 |shuzi:31|count_h2 (|shuzi:31|:162)
- 5 - B 05 DFFE 2 3 0 4 |shuzi:31|count_h1 (|shuzi:31|:163)
- 6 - B 05 DFFE 2 3 0 4 |shuzi:31|count_h0 (|shuzi:31|:164)
- 5 - B 01 OR2 0 4 0 4 |shuzi:31|:192
- 2 - B 07 OR2 0 4 0 1 |shuzi:31|:202
- 4 - B 10 OR2 0 4 0 1 |shuzi:31|:203
- 7 - B 10 OR2 0 3 0 1 |shuzi:31|:204
- 8 - B 07 OR2 0 4 0 4 |shuzi:31|:223
- 1 - B 10 OR2 0 4 0 5 |shuzi:31|:224
- 5 - B 10 OR2 0 4 0 4 |shuzi:31|:225
- 3 - B 10 OR2 0 4 0 5 |shuzi:31|:226
- 7 - B 07 OR2 0 4 0 2 |shuzi:31|:247
- 8 - B 03 AND2 s 0 2 0 2 |shuzi:31|~252~1
- 7 - B 11 OR2 0 4 0 2 |shuzi:31|:252
- 6 - B 11 OR2 0 4 0 2 |shuzi:31|:262
- 3 - B 03 OR2 0 4 0 2 |shuzi:31|:263
- 3 - B 07 DFFE 2 3 0 4 |shuzi:31|count_l3 (|shuzi:31|:272)
- 1 - B 11 DFFE 2 3 0 5 |shuzi:31|count_l2 (|shuzi:31|:273)
- 8 - B 11 DFFE 2 1 0 6 |shuzi:31|count_l1 (|shuzi:31|:274)
- 7 - B 03 DFFE 2 1 0 6 |shuzi:31|count_l0 (|shuzi:31|:275)
- 4 - B 01 OR2 0 4 0 6 |shuzi:31|:298
- 3 - B 01 OR2 0 4 0 3 |shuzi:31|:299
- 4 - B 05 OR2 0 3 0 4 |shuzi:31|:300
- 3 - B 05 OR2 0 3 0 4 |shuzi:31|:301
- 5 - B 07 DFFE 2 3 1 0 |shuzi:31|:545
- 3 - C 13 DFFE 2 1 1 0 |shuzi:31|:546
- 1 - B 05 DFFE 2 3 1 0 |shuzi:31|:547
- 8 - B 05 DFFE 2 3 1 0 |shuzi:31|:548
- 6 - B 07 DFFE 2 3 1 0 |shuzi:31|:549
- 4 - B 11 DFFE 2 3 1 0 |shuzi:31|:550
- 2 - B 11 DFFE 2 1 1 0 |shuzi:31|:551
- 1 - B 03 DFFE 2 1 1 0 |shuzi:31|:552
- 7 - A 14 DFFE 2 1 0 1 |weigui:4|alam_temp (|weigui:4|:24)
- 4 - A 14 DFFE 2 1 0 3 |weigui:4|three_temp (|weigui:4|:36)
- 1 - A 24 AND2 3 1 0 1 |youxianbianma:3|:70
- 3 - A 21 AND2 s 2 1 0 3 |youxianbianma:3|~71~1
- 8 - A 24 OR2 1 2 0 1 |youxianbianma:3|:121
- 2 - A 24 OR2 s 2 2 0 1 |youxianbianma:3|~131~1
- 5 - A 24 OR2 s 3 1 0 2 |youxianbianma:3|~132~1
- 7 - A 24 OR2 1 3 0 1 |youxianbianma:3|:132
- 1 - A 21 OR2 s 2 1 0 1 |youxianbianma:3|~133~1
- 3 - A 24 OR2 0 3 1 4 |youxianbianma:3|:135
- 4 - A 24 OR2 2 2 1 4 |youxianbianma:3|:136
- 6 - A 24 OR2 1 3 1 4 |youxianbianma:3|:137
- 2 - A 21 OR2 2 1 1 3 |youxianbianma:3|:138
- 1 - A 14 OR2 1 3 1 0 :25
- 4 - A 18 OR2 0 4 0 9 :26
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 17/ 96( 17%) 0/ 48( 0%) 30/ 48( 62%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
B: 12/ 96( 12%) 30/ 48( 62%) 27/ 48( 56%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 24/ 96( 25%) 22/ 48( 45%) 7/ 48( 14%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 5/24( 20%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 69 1hz
INPUT 2 1Khz
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** EQUATIONS **
a : INPUT;
b : INPUT;
c : INPUT;
clr : INPUT;
ctrl : INPUT;
d : INPUT;
down : INPUT;
up : INPUT;
1hz : INPUT;
1Khz : INPUT;
-- Node name is 'ALAM'
-- Equation name is 'ALAM', type is output
ALAM = _LC1_A14;
-- Node name is 'LED0'
-- Equation name is 'LED0', type is output
LED0 = _LC2_A21;
-- Node name is 'LED1'
-- Equation name is 'LED1', type is output
LED1 = _LC6_A24;
-- Node name is 'LED2'
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