📄 diceng.rpt
字号:
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V ^ S S S S S V G G G G V G S S S S S S S
C n H H H H H C N N N N C N H H H H H H H
C C U U U U U C D D D D C D U U U U U U U
I O Z Z Z Z Z I I I I I I I Z Z Z Z Z Z Z
N N 3 3 3 3 3 N N N N N N N 3 3 I I I I I
T F I I I I I T T T T T T T I I 2 2 2 2 2
I 1 2 3 4 5 6 7 I I I I I
G 0 1 2 3 4
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
A14 7/ 8( 87%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 4/22( 18%)
A15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
A16 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
A17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 11/22( 50%)
A18 5/ 8( 62%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
A19 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A20 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
A21 3/ 8( 37%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 3/22( 13%)
A23 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 8/22( 36%)
A24 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
B1 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
B3 6/ 8( 75%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
B5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
B7 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
B10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
B11 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 8/22( 36%)
B13 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
B15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
B16 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
B18 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
B19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B20 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
B22 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
C2 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
C5 7/ 8( 87%) 4/ 8( 50%) 2/ 8( 25%) 1/2 0/2 10/22( 45%)
C7 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
C9 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 10/22( 45%)
C10 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
C11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
C12 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
C13 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
C16 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 47/53 ( 88%)
Total logic cells used: 215/576 ( 37%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.27/4 ( 81%)
Total fan-in: 704/2304 ( 30%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 37
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 215
Total flipflops required: 70
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 16/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 2 7 8 7 8 5 8 8 3 0 8 8 72/0
B: 8 0 6 0 8 0 8 0 0 8 8 0 0 8 0 8 2 0 8 2 8 0 8 0 0 90/0
C: 0 8 0 0 7 0 2 0 8 2 8 8 0 2 0 0 8 0 0 0 0 0 0 0 0 53/0
Total: 8 8 6 0 15 0 10 0 8 10 16 8 0 12 7 16 17 8 13 10 16 3 8 8 8 215/0
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - - 03 INPUT 0 0 0 4 a
9 - - - 02 INPUT 0 0 0 5 b
10 - - - 01 INPUT 0 0 0 4 c
19 - - A -- INPUT 0 0 0 64 clr
16 - - A -- INPUT 0 0 0 6 ctrl
11 - - - 01 INPUT 0 0 0 2 d
18 - - A -- INPUT 0 0 0 4 down
17 - - A -- INPUT 0 0 0 4 up
5 - - - 05 INPUT 0 0 0 69 1hz
3 - - - 12 INPUT 0 0 0 2 1Khz
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - - 13 OUTPUT 0 1 0 0 ALAM
81 - - - 22 OUTPUT 0 1 0 0 LED0
79 - - - 24 OUTPUT 0 1 0 0 LED1
73 - - A -- OUTPUT 0 1 0 0 LED2
71 - - A -- OUTPUT 0 1 0 0 LED3
49 - - - 16 OUTPUT 0 1 0 0 SHUZI2I0
50 - - - 17 OUTPUT 0 1 0 0 SHUZI2I1
51 - - - 18 OUTPUT 0 1 0 0 SHUZI2I2
52 - - - 19 OUTPUT 0 1 0 0 SHUZI2I3
53 - - - 20 OUTPUT 0 1 0 0 SHUZI2I4
54 - - - 21 OUTPUT 0 1 0 0 SHUZI2I5
58 - - C -- OUTPUT 0 1 0 0 SHUZI2I6
59 - - C -- OUTPUT 0 1 0 0 SHUZI2I7
60 - - C -- OUTPUT 0 1 0 0 SHUZ1I0
61 - - C -- OUTPUT 0 1 0 0 SHUZ1I1
62 - - C -- OUTPUT 0 1 0 0 SHUZ1I2
64 - - B -- OUTPUT 0 1 0 0 SHUZ1I3
65 - - B -- OUTPUT 0 1 0 0 SHUZ1I4
66 - - B -- OUTPUT 0 1 0 0 SHUZ1I5
67 - - B -- OUTPUT 0 1 0 0 SHUZ1I6
69 - - A -- OUTPUT 0 1 0 0 SHUZ1I7
30 - - C -- OUTPUT 0 1 0 0 SHUZ3I0
35 - - - 06 OUTPUT 0 1 0 0 SHUZ3I1
36 - - - 07 OUTPUT 0 1 0 0 SHUZ3I2
37 - - - 09 OUTPUT 0 1 0 0 SHUZ3I3
38 - - - 10 OUTPUT 0 1 0 0 SHUZ3I4
39 - - - 11 OUTPUT 0 1 0 0 SHUZ3I5
47 - - - 14 OUTPUT 0 1 0 0 SHUZ3I6
48 - - - 15 OUTPUT 0 1 0 0 SHUZ3I7
21 - - B -- OUTPUT 0 1 0 0 SHUZ4I0
22 - - B -- OUTPUT 0 1 0 0 SHUZ4I1
23 - - B -- OUTPUT 0 1 0 0 SHUZ4I2
24 - - B -- OUTPUT 0 1 0 0 SHUZ4I3
25 - - B -- OUTPUT 0 1 0 0 SHUZ4I4
27 - - C -- OUTPUT 0 1 0 0 SHUZ4I5
28 - - C -- OUTPUT 0 1 0 0 SHUZ4I6
29 - - C -- OUTPUT 0 1 0 0 SHUZ4I7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\wodeshji\diceng.rpt
diceng
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 14 DFFE 1 0 0 1 |clk100_2:1|:182
- 3 - A 14 DFFE 1 2 0 2 |count3:2|c31 (|count3:2|:47)
- 2 - A 14 DFFE 1 2 0 2 |count3:2|c30 (|count3:2|:48)
- 6 - A 14 DFFE 1 3 0 1 |count3:2|:58
- 1 - A 19 OR2 0 2 0 3 |shuzi:28|lpm_add_sub:553|addcore:adder|pcarry1
- 7 - A 19 OR2 0 2 0 3 |shuzi:28|lpm_add_sub:553|addcore:adder|pcarry2
- 6 - A 15 AND2 0 2 0 1 |shuzi:28|lpm_add_sub:554|addcore:adder|:55
- 3 - A 20 OR2 0 3 0 1 |shuzi:28|lpm_add_sub:555|addcore:adder|pcarry2
- 4 - A 17 AND2 0 2 0 1 |shuzi:28|lpm_add_sub:556|addcore:adder|:55
- 2 - C 05 OR2 ! 1 1 0 14 |shuzi:28|:31
- 5 - A 20 AND2 s 0 2 0 3 |shuzi:28|~32~1
- 3 - A 18 AND2 1 1 0 6 |shuzi:28|:32
- 1 - A 16 OR2 0 2 0 1 |shuzi:28|:44
- 3 - A 15 OR2 ! 0 4 0 6 |shuzi:28|:61
- 4 - A 15 OR2 0 4 0 1 |shuzi:28|:79
- 2 - A 20 OR2 s ! 0 4 0 3 |shuzi:28|~103~1
- 3 - A 16 OR2 ! 0 3 0 5 |shuzi:28|:103
- 6 - A 19 OR2 0 4 0 2 |shuzi:28|:136
- 5 - A 19 OR2 0 3 0 2 |shuzi:28|:138
- 8 - A 19 OR2 0 4 0 2 |shuzi:28|:150
- 6 - A 17 DFFE 2 3 0 2 |shuzi:28|count_h3 (|shuzi:28|:161)
- 6 - A 13 DFFE 2 1 0 3 |shuzi:28|count_h2 (|shuzi:28|:162)
- 4 - A 19 DFFE 2 3 0 4 |shuzi:28|count_h1 (|shuzi:28|:163)
- 2 - A 19 DFFE 2 3 0 4 |shuzi:28|count_h0 (|shuzi:28|:164)
- 1 - A 17 OR2 0 4 0 4 |shuzi:28|:192
- 5 - A 15 OR2 0 4 0 1 |shuzi:28|:202
- 7 - A 15 OR2 0 4 0 1 |shuzi:28|:203
- 8 - A 15 OR2 0 3 0 1 |shuzi:28|:204
- 1 - A 20 OR2 0 4 0 4 |shuzi:28|:223
- 1 - A 15 OR2 0 4 0 5 |shuzi:28|:224
- 2 - A 15 OR2 0 4 0 4 |shuzi:28|:225
- 8 - A 20 OR2 0 4 0 5 |shuzi:28|:226
- 6 - A 20 OR2 0 4 0 2 |shuzi:28|:247
- 2 - A 16 AND2 s 0 2 0 2 |shuzi:28|~252~1
- 6 - A 23 OR2 0 4 0 2 |shuzi:28|:252
- 2 - A 23 OR2 0 4 0 2 |shuzi:28|:262
- 6 - A 16 OR2 0 4 0 2 |shuzi:28|:263
- 4 - A 20 DFFE 2 3 0 4 |shuzi:28|count_l3 (|shuzi:28|:272)
- 8 - A 23 DFFE 2 3 0 5 |shuzi:28|count_l2 (|shuzi:28|:273)
- 4 - A 23 DFFE 2 1 0 6 |shuzi:28|count_l1 (|shuzi:28|:274)
- 7 - A 16 DFFE 2 1 0 6 |shuzi:28|count_l0 (|shuzi:28|:275)
- 5 - A 17 OR2 0 4 0 6 |shuzi:28|:298
- 7 - A 17 OR2 0 4 0 3 |shuzi:28|:299
- 2 - A 17 OR2 0 3 0 4 |shuzi:28|:300
- 3 - A 17 OR2 0 3 0 4 |shuzi:28|:301
- 8 - A 17 DFFE 2 3 1 0 |shuzi:28|:545
- 1 - A 13 DFFE 2 1 1 0 |shuzi:28|:546
- 3 - A 19 DFFE 2 3 1 0 |shuzi:28|:547
- 5 - A 16 DFFE 2 3 1 0 |shuzi:28|:548
- 7 - A 20 DFFE 2 3 1 0 |shuzi:28|:549
- 1 - A 23 DFFE 2 3 1 0 |shuzi:28|:550
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