diceng.rpt

在FPGA上

Project Information                                     d:\wodeshji\diceng.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 07/02/2007 15:57:59

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

diceng    EPF10K10LC84-3   10     37     0    0         0  %    215      37 %

User Pins:                 10     37     0  



Project Information                                     d:\wodeshji\diceng.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

diceng@8                          a
diceng@83                         ALAM
diceng@9                          b
diceng@10                         c
diceng@19                         clr
diceng@16                         ctrl
diceng@11                         d
diceng@18                         down
diceng@81                         LED0
diceng@79                         LED1
diceng@73                         LED2
diceng@71                         LED3
diceng@49                         SHUZI2I0
diceng@50                         SHUZI2I1
diceng@51                         SHUZI2I2
diceng@52                         SHUZI2I3
diceng@53                         SHUZI2I4
diceng@54                         SHUZI2I5
diceng@58                         SHUZI2I6
diceng@59                         SHUZI2I7
diceng@60                         SHUZ1I0
diceng@61                         SHUZ1I1
diceng@62                         SHUZ1I2
diceng@64                         SHUZ1I3
diceng@65                         SHUZ1I4
diceng@66                         SHUZ1I5
diceng@67                         SHUZ1I6
diceng@69                         SHUZ1I7
diceng@30                         SHUZ3I0
diceng@35                         SHUZ3I1
diceng@36                         SHUZ3I2
diceng@37                         SHUZ3I3
diceng@38                         SHUZ3I4
diceng@39                         SHUZ3I5
diceng@47                         SHUZ3I6
diceng@48                         SHUZ3I7
diceng@21                         SHUZ4I0
diceng@22                         SHUZ4I1
diceng@23                         SHUZ4I2
diceng@24                         SHUZ4I3
diceng@25                         SHUZ4I4
diceng@27                         SHUZ4I5
diceng@28                         SHUZ4I6
diceng@29                         SHUZ4I7
diceng@17                         up
diceng@5                          1hz
diceng@3                          1Khz


Project Information                                     d:\wodeshji\diceng.rpt

** FILE HIERARCHY **



|clk100_2:1|
|clk100_2:1|lpm_add_sub:183|
|clk100_2:1|lpm_add_sub:183|addcore:adder|
|clk100_2:1|lpm_add_sub:183|altshift:result_ext_latency_ffs|
|clk100_2:1|lpm_add_sub:183|altshift:carry_ext_latency_ffs|
|clk100_2:1|lpm_add_sub:183|altshift:oflow_ext_latency_ffs|
|count3:2|
|count3:2|lpm_add_sub:59|
|count3:2|lpm_add_sub:59|addcore:adder|
|count3:2|lpm_add_sub:59|altshift:result_ext_latency_ffs|
|count3:2|lpm_add_sub:59|altshift:carry_ext_latency_ffs|
|count3:2|lpm_add_sub:59|altshift:oflow_ext_latency_ffs|
|youxianbianma:3|
|weigui:4|
|shuzi:31|
|shuzi:31|lpm_add_sub:553|
|shuzi:31|lpm_add_sub:553|addcore:adder|
|shuzi:31|lpm_add_sub:553|altshift:result_ext_latency_ffs|
|shuzi:31|lpm_add_sub:553|altshift:carry_ext_latency_ffs|
|shuzi:31|lpm_add_sub:553|altshift:oflow_ext_latency_ffs|
|shuzi:31|lpm_add_sub:554|
|shuzi:31|lpm_add_sub:554|addcore:adder|
|shuzi:31|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|shuzi:31|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|shuzi:31|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|shuzi:31|lpm_add_sub:555|
|shuzi:31|lpm_add_sub:555|addcore:adder|
|shuzi:31|lpm_add_sub:555|altshift:result_ext_latency_ffs|
|shuzi:31|lpm_add_sub:555|altshift:carry_ext_latency_ffs|
|shuzi:31|lpm_add_sub:555|altshift:oflow_ext_latency_ffs|
|shuzi:31|lpm_add_sub:556|
|shuzi:31|lpm_add_sub:556|addcore:adder|
|shuzi:31|lpm_add_sub:556|altshift:result_ext_latency_ffs|
|shuzi:31|lpm_add_sub:556|altshift:carry_ext_latency_ffs|
|shuzi:31|lpm_add_sub:556|altshift:oflow_ext_latency_ffs|
|shuzi:30|
|shuzi:30|lpm_add_sub:553|
|shuzi:30|lpm_add_sub:553|addcore:adder|
|shuzi:30|lpm_add_sub:553|altshift:result_ext_latency_ffs|
|shuzi:30|lpm_add_sub:553|altshift:carry_ext_latency_ffs|
|shuzi:30|lpm_add_sub:553|altshift:oflow_ext_latency_ffs|
|shuzi:30|lpm_add_sub:554|
|shuzi:30|lpm_add_sub:554|addcore:adder|
|shuzi:30|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|shuzi:30|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|shuzi:30|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|shuzi:30|lpm_add_sub:555|
|shuzi:30|lpm_add_sub:555|addcore:adder|
|shuzi:30|lpm_add_sub:555|altshift:result_ext_latency_ffs|
|shuzi:30|lpm_add_sub:555|altshift:carry_ext_latency_ffs|
|shuzi:30|lpm_add_sub:555|altshift:oflow_ext_latency_ffs|
|shuzi:30|lpm_add_sub:556|
|shuzi:30|lpm_add_sub:556|addcore:adder|
|shuzi:30|lpm_add_sub:556|altshift:result_ext_latency_ffs|
|shuzi:30|lpm_add_sub:556|altshift:carry_ext_latency_ffs|
|shuzi:30|lpm_add_sub:556|altshift:oflow_ext_latency_ffs|
|shuzi:29|
|shuzi:29|lpm_add_sub:553|
|shuzi:29|lpm_add_sub:553|addcore:adder|
|shuzi:29|lpm_add_sub:553|altshift:result_ext_latency_ffs|
|shuzi:29|lpm_add_sub:553|altshift:carry_ext_latency_ffs|
|shuzi:29|lpm_add_sub:553|altshift:oflow_ext_latency_ffs|
|shuzi:29|lpm_add_sub:554|
|shuzi:29|lpm_add_sub:554|addcore:adder|
|shuzi:29|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|shuzi:29|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|shuzi:29|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|shuzi:29|lpm_add_sub:555|
|shuzi:29|lpm_add_sub:555|addcore:adder|
|shuzi:29|lpm_add_sub:555|altshift:result_ext_latency_ffs|
|shuzi:29|lpm_add_sub:555|altshift:carry_ext_latency_ffs|
|shuzi:29|lpm_add_sub:555|altshift:oflow_ext_latency_ffs|
|shuzi:29|lpm_add_sub:556|
|shuzi:29|lpm_add_sub:556|addcore:adder|
|shuzi:29|lpm_add_sub:556|altshift:result_ext_latency_ffs|
|shuzi:29|lpm_add_sub:556|altshift:carry_ext_latency_ffs|
|shuzi:29|lpm_add_sub:556|altshift:oflow_ext_latency_ffs|
|shuzi:28|
|shuzi:28|lpm_add_sub:553|
|shuzi:28|lpm_add_sub:553|addcore:adder|
|shuzi:28|lpm_add_sub:553|altshift:result_ext_latency_ffs|
|shuzi:28|lpm_add_sub:553|altshift:carry_ext_latency_ffs|
|shuzi:28|lpm_add_sub:553|altshift:oflow_ext_latency_ffs|
|shuzi:28|lpm_add_sub:554|
|shuzi:28|lpm_add_sub:554|addcore:adder|
|shuzi:28|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|shuzi:28|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|shuzi:28|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|shuzi:28|lpm_add_sub:555|
|shuzi:28|lpm_add_sub:555|addcore:adder|
|shuzi:28|lpm_add_sub:555|altshift:result_ext_latency_ffs|
|shuzi:28|lpm_add_sub:555|altshift:carry_ext_latency_ffs|
|shuzi:28|lpm_add_sub:555|altshift:oflow_ext_latency_ffs|
|shuzi:28|lpm_add_sub:556|
|shuzi:28|lpm_add_sub:556|addcore:adder|
|shuzi:28|lpm_add_sub:556|altshift:result_ext_latency_ffs|
|shuzi:28|lpm_add_sub:556|altshift:carry_ext_latency_ffs|
|shuzi:28|lpm_add_sub:556|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                            d:\wodeshji\diceng.rpt
diceng

***** Logic for device 'diceng' compiled without errors.




Device: EPF10K10LC84-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                         ^     
                                                                         C     
                            R  R                             R     R     O     
                            E  E                             E     E     N     
                            S  S     V     G  G  G     G     S     S     F     
                            E  E     C     N  N  N     N     E     E     _  ^  
                            R  R     C  1  D  D  D  A  D  L  R  L  R  #  D  n  
                            V  V  1  I  K  I  I  I  L  I  E  V  E  V  T  O  C  
                            E  E  h  N  h  N  N  N  A  N  D  E  D  E  C  N  E  
                d  c  b  a  D  D  z  T  z  T  T  T  M  T  0  D  1  D  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | LED2 
      ^nCE | 14                                                              72 | RESERVED 
      #TDI | 15                                                              71 | LED3 
      ctrl | 16                                                              70 | RESERVED 
        up | 17                                                              69 | SHUZ1I7 
      down | 18                                                              68 | GNDINT 
       clr | 19                                                              67 | SHUZ1I6 
    VCCINT | 20                                                              66 | SHUZ1I5 
   SHUZ4I0 | 21                                                              65 | SHUZ1I4 
   SHUZ4I1 | 22                        EPF10K10LC84-3                        64 | SHUZ1I3 
   SHUZ4I2 | 23                                                              63 | VCCINT 
   SHUZ4I3 | 24                                                              62 | SHUZ1I2 
   SHUZ4I4 | 25                                                              61 | SHUZ1I1 
    GNDINT | 26                                                              60 | SHUZ1I0 
   SHUZ4I5 | 27                                                              59 | SHUZI2I7 
   SHUZ4I6 | 28                                                              58 | SHUZI2I6 
   SHUZ4I7 | 29                                                              57 | #TMS 
   SHUZ3I0 | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | SHUZI2I5