jishuqi2.v

来自「在FPGA上」· Verilog 代码 · 共 28 行

module	jishuqi2(clr,reset,up,down,shuzi);
	input	reset,up,down,clr;
	output[7:0]	shuzi;
	reg[4:0]	shuzil,shuzih;
	reg clkb,cout;
always @(posedge up or posedge clr)
    begin
 		if(clr) shuzil='b00000;
			else if(reset)
				if(shuzil[3:0]=='b1001) shuzil='b10000;
					else if(shuzil[3:0]<'b1001)
					begin shuzil=shuzil+1;shuzil[4]='b0;end
		clkb=shuzil[4];
 	end
	assign shuzi[3:0]=shuzil[3:0];
always @(posedge clkb or posedge clr)
	begin
		if(clr) shuzih='b00001;
			else if(reset)	
					if(shuzih[3:0]=='b1001)shuzih='b10000;
						else if(shuzih[3:0]<'b1001)
					begin shuzih[4]='b0;shuzih=shuzih+1;end
	end
	assign shuzi[7:4]=shuzih[3:0];
endmodule