jishuqi3.v

在FPGA上

module	jishuqi3(clr,reset,up,down,shuzi);
	input	reset,up,down,clr;
	output[7:0]	shuzi;
	reg[5:0]	shuzil,shuzih;
	reg clkbu,clkbd;
always @(posedge up or posedge clr or posedge down)
    begin
 		if(clr) shuzil='b00000;
			else if(reset)
					if(up)
					begin
				if(shuzil[3:0]=='b1001) shuzil='b010000;
					else if(shuzil[3:0]<'b1001)
					begin shuzil=shuzil+1;shuzil[4]='b0;end
		clkbu=shuzil[4];
					end
					else if(down)				
				if(shuzil[3:0]=='b00000) shuzil='b101001;
					else if (shuzil[3:0]>'b0000)
					begin shuzi[5]='b0;shuzil=shuzil-1;end		
		clkbd=shuzil[5];
 	end
	assign shuzi[3:0]=shuzil[3:0];
always @(posedge clkbu or posedge clr or clkbd)
	begin
		if(clr) shuzih='b00001;
			else if(reset)	
					if(clkbu)
					begin
					if(shuzih[3:0]=='b1001)shuzih='b010000;
						else if(shuzih[3:0]<'b1001)
					begin shuzih[4]='b0;shuzih=shuzih+1;end
					end
					else if(clkbd)
					if(shuzih[3:0]=='b0000)shuzih='b101001;
						else if(shuzih[3:0]>'b0000)
					begin shuzih[5]='b0;shuzih=shuzih-1;end
	end
	assign shuzi[7:4]=shuzih[3:0];
endmodule