weigui.v

来自「在FPGA上」· Verilog 代码 · 共 20 行

module weigui(ctrl,int,alam,clk,three) ;
output alam,three;
input ctrl,int,clk;
reg alam_temp,three_temp;
assign alam=alam_temp;
assign three=three_temp;

always @(posedge clk)
begin
  if((!ctrl)&&int)
    begin alam_temp=1;three_temp=0;end
  else if(ctrl&&int)
    begin three_temp=1;alam_temp=0;end
  else if((!ctrl)&&(!int))
	begin three_temp=0;alam_temp=0;end

end

endmodule