📄 jishuqi2.rpt
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Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi2.rpt
jishuqi2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 up
DFF 4 clkb
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi2.rpt
jishuqi2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 10 clr
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi2.rpt
jishuqi2
** EQUATIONS **
clr : INPUT;
reset : INPUT;
up : INPUT;
-- Node name is ':295' = 'clkb'
-- Equation name is 'clkb', location is LC6_B23, type is buried.
clkb = DFFE( _EQ001, GLOBAL( up), VCC, VCC, VCC);
_EQ001 = !clr & _LC4_B23 & reset
# !clr & !reset & shuzil4;
-- Node name is ':531' = 'shuzih0'
-- Equation name is 'shuzih0', location is LC1_B5, type is buried.
!shuzih0 = shuzih0~NOT;
shuzih0~NOT = DFFE( _EQ002, clkb, GLOBAL(!clr), VCC, reset);
_EQ002 = _LC3_B5
# !_LC4_B5;
-- Node name is ':530' = 'shuzih1'
-- Equation name is 'shuzih1', location is LC6_B5, type is buried.
shuzih1 = DFFE( _EQ003, clkb, GLOBAL(!clr), VCC, reset);
_EQ003 = !_LC3_B5 & _LC7_B5;
-- Node name is ':529' = 'shuzih2'
-- Equation name is 'shuzih2', location is LC2_B5, type is buried.
shuzih2 = DFFE( _EQ004, clkb, GLOBAL(!clr), VCC, reset);
_EQ004 = !_LC3_B5 & _LC8_B5;
-- Node name is ':528' = 'shuzih3'
-- Equation name is 'shuzih3', location is LC8_B23, type is buried.
shuzih3 = DFFE( _LC5_B5, clkb, GLOBAL(!clr), VCC, reset);
-- Node name is ':248' = 'shuzil0'
-- Equation name is 'shuzil0', location is LC3_B23, type is buried.
shuzil0 = DFFE( _EQ005, GLOBAL( up), GLOBAL(!clr), VCC, reset);
_EQ005 = !_LC1_B23 & _LC7_B23;
-- Node name is ':247' = 'shuzil1'
-- Equation name is 'shuzil1', location is LC1_B15, type is buried.
shuzil1 = DFFE( _LC2_B15, GLOBAL( up), GLOBAL(!clr), VCC, reset);
-- Node name is ':246' = 'shuzil2'
-- Equation name is 'shuzil2', location is LC5_B15, type is buried.
shuzil2 = DFFE( _LC3_B15, GLOBAL( up), GLOBAL(!clr), VCC, reset);
-- Node name is ':245' = 'shuzil3'
-- Equation name is 'shuzil3', location is LC7_B15, type is buried.
shuzil3 = DFFE( _LC4_B15, GLOBAL( up), GLOBAL(!clr), VCC, reset);
-- Node name is ':244' = 'shuzil4'
-- Equation name is 'shuzil4', location is LC5_B23, type is buried.
shuzil4 = DFFE( _LC4_B23, GLOBAL( up), GLOBAL(!clr), VCC, reset);
-- Node name is 'shuzi0'
-- Equation name is 'shuzi0', type is output
shuzi0 = shuzil0;
-- Node name is 'shuzi1'
-- Equation name is 'shuzi1', type is output
shuzi1 = shuzil1;
-- Node name is 'shuzi2'
-- Equation name is 'shuzi2', type is output
shuzi2 = shuzil2;
-- Node name is 'shuzi3'
-- Equation name is 'shuzi3', type is output
shuzi3 = shuzil3;
-- Node name is 'shuzi4'
-- Equation name is 'shuzi4', type is output
shuzi4 = shuzih0;
-- Node name is 'shuzi5'
-- Equation name is 'shuzi5', type is output
shuzi5 = shuzih1;
-- Node name is 'shuzi6'
-- Equation name is 'shuzi6', type is output
shuzi6 = shuzih2;
-- Node name is 'shuzi7'
-- Equation name is 'shuzi7', type is output
shuzi7 = shuzih3;
-- Node name is ':16'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ006);
_EQ006 = shuzil0 & !shuzil1 & !shuzil2 & shuzil3;
-- Node name is ':195'
-- Equation name is '_LC2_B23', type is buried
!_LC2_B23 = _LC2_B23~NOT;
_LC2_B23~NOT = LCELL( _EQ007);
_EQ007 = shuzil0 & shuzil3
# shuzil2 & shuzil3
# shuzil1 & shuzil3;
-- Node name is ':234'
-- Equation name is '_LC4_B15', type is buried
_LC4_B15 = LCELL( _EQ008);
_EQ008 = shuzil2 & shuzil3
# shuzil1 & shuzil3
# !shuzil0 & shuzil3
# shuzil0 & shuzil1 & shuzil2;
-- Node name is ':235'
-- Equation name is '_LC3_B15', type is buried
_LC3_B15 = LCELL( _EQ009);
_EQ009 = !shuzil1 & shuzil2
# !shuzil0 & shuzil2
# shuzil0 & shuzil1 & !shuzil2 & !shuzil3
# shuzil2 & shuzil3;
-- Node name is ':236'
-- Equation name is '_LC2_B15', type is buried
_LC2_B15 = LCELL( _EQ010);
_EQ010 = !shuzil0 & shuzil1
# shuzil0 & !shuzil1 & !shuzil3
# shuzil1 & shuzil3;
-- Node name is '~237~1'
-- Equation name is '~237~1', location is LC7_B23, type is buried.
-- synthesized logic cell
_LC7_B23 = LCELL( _EQ011);
_EQ011 = shuzil0 & shuzil3
# !shuzil0 & !shuzil1 & !shuzil2
# !shuzil0 & !shuzil3;
-- Node name is ':238'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ012);
_EQ012 = _LC1_B23
# !_LC2_B23 & shuzil4;
-- Node name is ':299'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = LCELL( _EQ013);
_EQ013 = shuzih0 & !shuzih1 & !shuzih2 & shuzih3;
-- Node name is ':513'
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = LCELL( _EQ014);
_EQ014 = !shuzih1 & shuzih2
# !shuzih0 & shuzih2
# shuzih0 & shuzih1 & !shuzih2 & !shuzih3
# shuzih2 & shuzih3;
-- Node name is ':514'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = LCELL( _EQ015);
_EQ015 = !shuzih0 & shuzih1
# shuzih0 & !shuzih1 & !shuzih3
# shuzih1 & shuzih3;
-- Node name is ':517'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ016);
_EQ016 = shuzih0 & shuzih1 & shuzih2
# shuzih2 & shuzih3
# shuzih1 & shuzih3
# !shuzih0 & shuzih3;
-- Node name is '~520~1'
-- Equation name is '~520~1', location is LC4_B5, type is buried.
-- synthesized logic cell
!_LC4_B5 = _LC4_B5~NOT;
_LC4_B5~NOT = LCELL( _EQ017);
_EQ017 = shuzih0 & !shuzih3
# !shuzih0 & shuzih2 & shuzih3
# !shuzih0 & shuzih1 & shuzih3;
Project Information d:\tools\altera.max.plus.ii\wodeshji\jishuqi2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,664K
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