youxianbianma.rpt

在FPGA上

        | | | | | | | +--------- LC21 ~135~1
        | | | | | | | | +------- LC22 ~136~1
        | | | | | | | | | +----- LC23 ~137~1
        | | | | | | | | | | +--- LC24 ~138~1
        | | | | | | | | | | | +- LC30 ~139~1
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> - - - - * * * - * * * - | - * | <-- led0
LC18 -> - - - - * * * - * * * - | - * | <-- led1
LC19 -> - - - - * * * - * * * - | - * | <-- led2
LC29 -> - - - * - - - * - - - - | - * | <-- ~70~1
LC25 -> - - - - - - * - * * * - | - * | <-- ~93~1
LC20 -> - - - * - - - * - - - - | - * | <-- ~131~1
LC21 -> - - - - - - * - - - - * | - * | <-- ~135~1
LC22 -> - - * - - - - - * - - - | - * | <-- ~136~1
LC23 -> - * - - - - - - - * - - | - * | <-- ~137~1
LC24 -> * - - - - - - - - - * - | - * | <-- ~138~1
LC30 -> - - - - * * * - * * * - | - * | <-- ~139~1

Pin
4    -> - - - - * - * - * * * - | - * | <-- a
5    -> - - - - * - * - * * * - | - * | <-- b
6    -> - - - - * - * - * * * - | - * | <-- c
7    -> - - - - * - * - * * * - | - * | <-- ctrl
8    -> - - - - * * - - - - - - | - * | <-- d


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:d:\tools\altera.max.plus.ii\wodeshji\youxianbianma.rpt
youxianbianma

** EQUATIONS **

a        : INPUT;
b        : INPUT;
c        : INPUT;
ctrl     : INPUT;
d        : INPUT;

-- Node name is 'led0' = '~142~1' 
-- Equation name is 'led0', location is LC017, type is output.
 led0    = LCELL( _LC024 $  GND);

-- Node name is 'led1' = '~141~1' 
-- Equation name is 'led1', location is LC018, type is output.
 led1    = LCELL( _LC023 $  GND);

-- Node name is 'led2' = '~140~1' 
-- Equation name is 'led2', location is LC019, type is output.
 led2    = LCELL( _LC022 $  GND);

-- Node name is 'led3' 
-- Equation name is 'led3', location is LC026, type is output.
 led3    = LCELL( _EQ001 $  VCC);
  _EQ001 = !_LC020 & !_LC029;

-- Node name is '~70~1' 
-- Equation name is '~70~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ002 $  GND);
  _EQ002 = !a & !b & !c & !ctrl &  d & !_LC030 & !led0
         # !ctrl &  d & !_LC030 & !led0 &  led1
         # !ctrl &  d & !_LC030 & !led0 &  led2;

-- Node name is '~93~1' 
-- Equation name is '~93~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ003 $  GND);
  _EQ003 =  d & !_LC030 & !led0 & !led1 & !led2;

-- Node name is '~131~1' 
-- Equation name is '~131~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ004 $  ctrl);
  _EQ004 =  a &  ctrl & !_LC030 & !led0 & !led1 & !led2
         #  b &  ctrl & !_LC030 & !led0 & !led1 & !led2
         #  c &  ctrl & !_LC030 & !led0 & !led1 & !led2
         #  ctrl & !_LC021 & !_LC025;

-- Node name is '~135~1' 
-- Equation name is '~135~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ005 $  VCC);
  _EQ005 = !_LC020 & !_LC029;

-- Node name is '~136~1' 
-- Equation name is '~136~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ006 $  GND);
  _EQ006 = !a & !b &  c & !_LC030 & !led0 & !led1 & !led2
         # !a & !b &  ctrl &  _LC022 & !_LC025
         #  ctrl &  _LC022 & !_LC025 &  _X001;
  _X001  = EXP(!_LC030 & !led0 & !led1 & !led2);

-- Node name is '~137~1' 
-- Equation name is '~137~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ007 $  GND);
  _EQ007 = !a &  b & !_LC030 & !led0 & !led1 & !led2
         # !a & !c &  ctrl &  _LC023 & !_LC025
         #  ctrl &  _LC023 & !_LC025 &  _X001;
  _X001  = EXP(!_LC030 & !led0 & !led1 & !led2);

-- Node name is '~138~1' 
-- Equation name is '~138~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ008 $  GND);
  _EQ008 = !b & !c &  ctrl &  _LC024 & !_LC025
         #  a & !_LC030 & !led0 & !led1 & !led2
         #  ctrl &  _LC024 & !_LC025 &  _X001;
  _X001  = EXP(!_LC030 & !led0 & !led1 & !led2);

-- Node name is '~139~1' 
-- Equation name is '~139~1', location is LC030, type is buried.
-- synthesized logic cell 
_LC030   = LCELL( _LC021 $  GND);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information     d:\tools\altera.max.plus.ii\wodeshji\youxianbianma.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,192K