jishuqi.v

来自「在FPGA上」· Verilog 代码 · 共 47 行

module	jishuqi(ld,start,up,down,shuzil,shuzih);
input	start,up,down,ld;
output[3:0]	shuzil,shuzih;
reg[3:0]	shuzil,shuzih;
//wire	start,up,down,ld;

always @ (posedge ld or posedge up or posedge down)
begin
  if(ld==1)
  begin
  shuzil<=4'b0;
  shuzih<=4'b1;
  end
  if(start==1)
  begin
    	if(up==1)
   		begin
     	 if(shuzil==4'b1001)  
     	 	begin
     	 	shuzil<=4'b0;
         	if(shuzih==4'b1001)
				begin
         		shuzih<=4'b0;
				end
         	else shuzih<=shuzih+1;
      		end
      	else shuzil<=shuzil+1;
		end
   		else if(down==1)
   		begin
     	if(shuzil==4'b0)
    		begin
       		if(shuzih==4'b0)
	   			begin
       			shuzih<=4'b0;
       			shuzil<=4'b0;
       			end
	  		else shuzih<=shuzih-1;
	        shuzil<=4'b1001;
     	end
       	else shuzil<=shuzil-1;
  end
end 
end 
endmodule