jishuqi.rpt

在FPGA上

-- Equation name is '_LC063', type is buried 
_LC063   = LCELL( shuzih3 $  _EQ015);
  _EQ015 =  shuzih0 &  shuzih1 &  shuzih2;

-- Node name is '|lpm_add_sub:231|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC045', type is buried 
_LC045   = LCELL( _EQ016 $  shuzih2);
  _EQ016 =  shuzih1 & !shuzih2;

-- Node name is '|lpm_add_sub:231|addcore:adder|addcore:adder0|pp0~1' from file "addcore.tdf" line 328, column 22
-- Equation name is '_LC053', type is buried 
-- synthesized logic cell 
_LC053   = LCELL(!shuzih0 $  GND);

-- Node name is '|lpm_add_sub:231|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried 
_LC050   = LCELL( shuzih3 $  _EQ017);
  _EQ017 = !_LC045 &  _LC053;

-- Node name is '~109~1' 
-- Equation name is '~109~1', location is LC041, type is buried.
-- synthesized logic cell 
_LC041   = LCELL( _EQ018 $  GND);
  _EQ018 = !ld &  shuzil0 & !start;

-- Node name is '~110~1~2' 
-- Equation name is '~110~1~2', location is LC042, type is buried.
-- synthesized logic cell 
_LC042   = LCELL( _EQ019 $  GND);
  _EQ019 =  down &  _LC064 & !shuzil0 & !shuzil1 & !shuzil2 & !shuzil3 & 
              start &  _X017
         #  down &  _LC038 &  _LC064 &  start &  _X017
         # !down &  _LC064 & !ld &  shuzil3 &  start &  _X017
         #  _LC064 & !ld &  shuzil3 &  up &  _X017
         #  _LC038 & !ld &  shuzil3 &  start & !up;
  _X017  = EXP( shuzil0 & !shuzil1 & !shuzil2 &  shuzil3);

-- Node name is '~110~1~3' 
-- Equation name is '~110~1~3', location is LC043, type is buried.
-- synthesized logic cell 
_LC043   = LCELL( _EQ020 $  GND);
  _EQ020 =  down &  _LC038 & !ld &  shuzil3 & !up
         # !ld &  shuzil3 & !start
         #  _LC042;

-- Node name is '~111~1~2' 
-- Equation name is '~111~1~2', location is LC044, type is buried.
-- synthesized logic cell 
_LC044   = LCELL( _EQ021 $  GND);
  _EQ021 =  down &  _LC039 &  _LC060 &  start &  _X016 &  _X017
         #  _LC039 & !ld &  shuzil2 &  start & !up &  _X016
         #  down &  _LC039 & !ld &  shuzil2 & !up &  _X016
         # !down &  _LC060 & !ld &  shuzil2 &  start &  _X017
         #  _LC060 & !ld &  shuzil2 &  up &  _X017;
  _X016  = EXP(!shuzil0 & !shuzil1 & !shuzil2 & !shuzil3);
  _X017  = EXP( shuzil0 & !shuzil1 & !shuzil2 &  shuzil3);

-- Node name is '~112~1~2' 
-- Equation name is '~112~1~2', location is LC046, type is buried.
-- synthesized logic cell 
_LC046   = LCELL( _EQ022 $  GND);
  _EQ022 =  down &  _LC034 &  _LC047 &  start &  _X016 &  _X017
         #  _LC047 & !ld &  shuzil1 &  start & !up &  _X016
         #  down &  _LC047 & !ld &  shuzil1 & !up &  _X016
         # !down &  _LC034 & !ld &  shuzil1 &  start &  _X017
         #  _LC034 & !ld &  shuzil1 &  up &  _X017;
  _X016  = EXP(!shuzil0 & !shuzil1 & !shuzil2 & !shuzil3);
  _X017  = EXP( shuzil0 & !shuzil1 & !shuzil2 &  shuzil3);

-- Node name is '~113~1~2' 
-- Equation name is '~113~1~2', location is LC057, type is buried.
-- synthesized logic cell 
_LC057   = LCELL( _EQ023 $  GND);
  _EQ023 =  _LC018 & !_LC041 & !ld &  shuzil0 &  start & !up
         #  down &  _LC018 & !_LC041 & !shuzil0 &  start
         # !_LC041 & !shuzil0 &  start &  up;

-- Node name is '~224~2' 
-- Equation name is '~224~2', location is LC059, type is buried.
-- synthesized logic cell 
_LC059   = LCELL( _EQ024 $  GND);
  _EQ024 =  down &  _LC050 &  shuzih0 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up
         #  down &  _LC050 &  shuzih1 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up
         #  down &  _LC050 &  shuzih2 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up
         #  down &  _LC050 &  shuzih3 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up
         #  _LC063 &  shuzih1 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up;

-- Node name is '~224~3' 
-- Equation name is '~224~3', location is LC061, type is buried.
-- synthesized logic cell 
_LC061   = LCELL( _EQ025 $  GND);
  _EQ025 =  _LC063 &  shuzih2 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up
         #  _LC063 & !shuzih0 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up
         #  _LC063 & !shuzih3 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up
         # !ld &  shuzih3 & !shuzil0 &  shuzil3
         # !ld &  shuzih3 & !shuzil3 &  up;

-- Node name is '~225~2' 
-- Equation name is '~225~2', location is LC054, type is buried.
-- synthesized logic cell 
_LC054   = LCELL( _EQ026 $  GND);
  _EQ026 =  down &  _LC053 & !shuzih1 & !shuzih2 &  shuzih3 & !shuzil0 & 
             !shuzil1 & !shuzil2 & !shuzil3 &  start & !up
         #  down &  _LC053 &  shuzih0 & !shuzih1 & !shuzih2 & !shuzil0 & 
             !shuzil1 & !shuzil2 & !shuzil3 &  start & !up
         #  shuzih0 &  shuzih1 & !shuzih2 &  shuzil0 & !shuzil1 & !shuzil2 & 
              shuzil3 &  start &  up
         #  down &  shuzih1 &  shuzih2 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up
         #  down & !_LC053 &  shuzih2 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up;

-- Node name is '~225~3' 
-- Equation name is '~225~3', location is LC055, type is buried.
-- synthesized logic cell 
_LC055   = LCELL( _EQ027 $  GND);
  _EQ027 = !shuzih1 &  shuzih2 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up
         # !shuzih0 &  shuzih2 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up
         # !ld &  shuzih2 & !shuzil3 &  up
         # !ld &  shuzih2 &  shuzil0 & !up
         # !ld &  shuzih2 & !shuzil0 &  shuzil3;

-- Node name is '~226~2' 
-- Equation name is '~226~2', location is LC056, type is buried.
-- synthesized logic cell 
_LC056   = LCELL( _EQ028 $  GND);
  _EQ028 =  down &  _LC053 & !shuzih1 &  shuzih3 & !shuzil0 & !shuzil1 & 
             !shuzil2 & !shuzil3 &  start & !up
         #  down &  _LC053 &  shuzih0 & !shuzih1 & !shuzil0 & !shuzil1 & 
             !shuzil2 & !shuzil3 &  start & !up
         #  down &  _LC053 & !shuzih1 &  shuzih2 & !shuzil0 & !shuzil1 & 
             !shuzil2 & !shuzil3 &  start & !up
         #  shuzih0 & !shuzih1 &  shuzih2 &  shuzil0 & !shuzil1 & !shuzil2 & 
              shuzil3 &  start &  up
         #  shuzih0 & !shuzih1 & !shuzih3 &  shuzil0 & !shuzil1 & !shuzil2 & 
              shuzil3 &  start &  up;

-- Node name is '~226~3' 
-- Equation name is '~226~3', location is LC058, type is buried.
-- synthesized logic cell 
_LC058   = LCELL( _EQ029 $  GND);
  _EQ029 =  down & !_LC053 &  shuzih1 & !shuzil0 & !shuzil1 & !shuzil2 & 
             !shuzil3 &  start & !up
         # !shuzih0 &  shuzih1 &  shuzil0 & !shuzil1 & !shuzil2 &  shuzil3 & 
              start &  up
         # !ld &  shuzih1 & !shuzil0 &  up
         # !ld &  shuzih1 &  shuzil3 & !up
         # !ld &  shuzih1 &  shuzil0 & !shuzil3;

-- Node name is '~227~2' 
-- Equation name is '~227~2', location is LC062, type is buried.
-- synthesized logic cell 
_LC062   = LCELL( _EQ030 $  GND);
  _EQ030 = !ld & !shuzih0 & !shuzil0 &  shuzil3
         # !ld & !shuzih0 &  shuzil0 & !up
         # !ld & !shuzih0 & !shuzil3 &  up
         # !down & !ld & !shuzih0 & !up
         # !ld & !shuzih0 &  shuzil2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information           d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,757K