📄 jishuqi.rpt
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| Other LABs fed by signals
| that feed LAB 'B'
LC | | A B C D | Logic cells that feed LAB 'B':
Pin
LC49 -> * | - * * * | <-- shuzil0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC34 |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node1
| +----------------------------- LC48 |lpm_add_sub:229|addcore:adder|addcore:adder0|gcp2
| | +--------------------------- LC47 |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node1
| | | +------------------------- LC39 |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node2
| | | | +----------------------- LC38 |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node3
| | | | | +--------------------- LC45 |lpm_add_sub:231|addcore:adder|addcore:adder0|gcp2
| | | | | | +------------------- LC33 shuzih1
| | | | | | | +----------------- LC35 shuzih2
| | | | | | | | +--------------- LC40 shuzil1
| | | | | | | | | +------------- LC37 shuzil2
| | | | | | | | | | +----------- LC36 shuzil3
| | | | | | | | | | | +--------- LC41 ~109~1
| | | | | | | | | | | | +------- LC42 ~110~1~2
| | | | | | | | | | | | | +----- LC43 ~110~1~3
| | | | | | | | | | | | | | +--- LC44 ~111~1~2
| | | | | | | | | | | | | | | +- LC46 ~112~1~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC34 -> - - - - - - - - * - - - - - - * | - - * - | <-- |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node1
LC48 -> - - - - * - - - - - - - - - - - | - - * - | <-- |lpm_add_sub:229|addcore:adder|addcore:adder0|gcp2
LC47 -> - - - - - - - - * - - - - - - * | - - * - | <-- |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node1
LC39 -> - - - - - - - - - * - - - - * - | - - * - | <-- |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node2
LC38 -> - - - - - - - - - - * - * * - - | - - * - | <-- |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node3
LC33 -> - - - - - * * - - - - - - - - - | - - * * | <-- shuzih1
LC35 -> - - - - - * - * - - - - - - - - | - - * * | <-- shuzih2
LC40 -> * * * * - - * * * * * - * - * * | - - * * | <-- shuzil1
LC37 -> - * - * - - * * * * * - * - * * | - - * * | <-- shuzil2
LC36 -> - - - - * - - - * * * - * * * * | - - * * | <-- shuzil3
LC42 -> - - - - - - - - - - - - - * - - | - - * - | <-- ~110~1~2
LC43 -> - - - - - - - - - - * - - - - - | - - * - | <-- ~110~1~3
LC44 -> - - - - - - - - - * - - - - - - | - - * - | <-- ~111~1~2
LC46 -> - - - - - - - - * - - - - - - - | - - * - | <-- ~112~1~2
Pin
12 -> - - - - - - * * * * * - * * * * | - - * * | <-- down
11 -> - - - - - - * * * * * * * * * * | - - * * | <-- ld
8 -> - - - - - - * * * * * * * * * * | - - * * | <-- start
9 -> - - - - - - - - * * * - * * * * | - - * * | <-- up
LC60 -> - - - - - - - - - * - - - - * - | - - * - | <-- |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node2
LC64 -> - - - - - - - - - - * - * - - - | - - * - | <-- |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node3
LC18 -> - - * * * - - - - - - - - - - - | - - * * | <-- |lpm_add_sub:229|addcore:adder|addcore:adder0|pp0~1
LC49 -> * - - - - - * * * * * * * - * * | - * * * | <-- shuzil0
LC54 -> - - - - - - - * - - - - - - - - | - - * - | <-- ~225~2
LC55 -> - - - - - - - * - - - - - - - - | - - * - | <-- ~225~3
LC56 -> - - - - - - * - - - - - - - - - | - - * - | <-- ~226~2
LC58 -> - - - - - - * - - - - - - - - - | - - * - | <-- ~226~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC60 |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node2
| +----------------------------- LC64 |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node3
| | +--------------------------- LC63 |lpm_add_sub:230|addcore:adder|addcore:adder0|result_node3
| | | +------------------------- LC53 |lpm_add_sub:231|addcore:adder|addcore:adder0|pp0~1
| | | | +----------------------- LC50 |lpm_add_sub:231|addcore:adder|addcore:adder0|result_node3
| | | | | +--------------------- LC51 shuzih0
| | | | | | +------------------- LC52 shuzih3
| | | | | | | +----------------- LC49 shuzil0
| | | | | | | | +--------------- LC57 ~113~1~2
| | | | | | | | | +------------- LC59 ~224~2
| | | | | | | | | | +----------- LC61 ~224~3
| | | | | | | | | | | +--------- LC54 ~225~2
| | | | | | | | | | | | +------- LC55 ~225~3
| | | | | | | | | | | | | +----- LC56 ~226~2
| | | | | | | | | | | | | | +--- LC58 ~226~3
| | | | | | | | | | | | | | | +- LC62 ~227~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC63 -> - - - - - - - - - * * - - - - - | - - - * | <-- |lpm_add_sub:230|addcore:adder|addcore:adder0|result_node3
LC53 -> - - - - * * - - - - - * - * * - | - - - * | <-- |lpm_add_sub:231|addcore:adder|addcore:adder0|pp0~1
LC50 -> - - - - - - - - - * - - - - - - | - - - * | <-- |lpm_add_sub:231|addcore:adder|addcore:adder0|result_node3
LC51 -> - - * * - * - - - * * * * * * * | - - - * | <-- shuzih0
LC52 -> - - * - * * * - - * * * - * - - | - - - * | <-- shuzih3
LC49 -> * * - - - * * * * * * * * * * * | - * * * | <-- shuzil0
LC57 -> - - - - - - - * - - - - - - - - | - - - * | <-- ~113~1~2
LC59 -> - - - - - - * - - - - - - - - - | - - - * | <-- ~224~2
LC61 -> - - - - - - * - - - - - - - - - | - - - * | <-- ~224~3
LC62 -> - - - - - * - - - - - - - - - - | - - - * | <-- ~227~2
Pin
12 -> - - - - - * * * * * - * - * * * | - - * * | <-- down
11 -> - - - - - * * * * - * - * - * * | - - * * | <-- ld
8 -> - - - - - * * * * * * * * * * - | - - * * | <-- start
9 -> - - - - - * * * * * * * * * * * | - - * * | <-- up
LC18 -> - - - - - - - * * - - - - - - - | - - * * | <-- |lpm_add_sub:229|addcore:adder|addcore:adder0|pp0~1
LC45 -> - - - - * - - - - - - - - - - - | - - - * | <-- |lpm_add_sub:231|addcore:adder|addcore:adder0|gcp2
LC33 -> - - * - - * - - - * - * * * * - | - - * * | <-- shuzih1
LC35 -> - - * - - * - - - * * * * * - - | - - * * | <-- shuzih2
LC40 -> * * - - - * * * - * * * * * * - | - - * * | <-- shuzil1
LC37 -> * * - - - * * * - * * * * * * * | - - * * | <-- shuzil2
LC36 -> - * - - - * - * - * * * * * * * | - - * * | <-- shuzil3
LC41 -> - - - - - - - * * - - - - - - - | - - - * | <-- ~109~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** EQUATIONS **
down : INPUT;
ld : INPUT;
start : INPUT;
up : INPUT;
-- Node name is 'shuzih0' = '~227~1'
-- Equation name is 'shuzih0', location is LC051, type is output.
shuzih0 = LCELL( _EQ001 $ _EQ002);
_EQ001 = down & !_LC062 & !shuzih0 & !shuzih1 & !shuzih2 & !shuzih3 &
!shuzil0 & !shuzil1 & !shuzil2 & !shuzil3 & start & !up &
_X001 & _X002
# down & !_LC053 & !_LC062 & !shuzil0 & !shuzil1 & !shuzil2 &
!shuzil3 & start & !up & _X001 & _X002
# !_LC062 & shuzih0 & shuzil0 & !shuzil1 & !shuzil2 & shuzil3 &
start & up & _X001 & _X002
# !_LC062 & !ld & !shuzih0 & !shuzih1 & !shuzih2 & !shuzih3 & !up &
_X001 & _X002;
_X001 = EXP(!ld & !shuzih0 & shuzil1);
_X002 = EXP(!ld & !shuzih0 & !start);
_EQ002 = !_LC062 & _X001 & _X002;
_X001 = EXP(!ld & !shuzih0 & shuzil1);
_X002 = EXP(!ld & !shuzih0 & !start);
-- Node name is 'shuzih1' = '~226~1'
-- Equation name is 'shuzih1', location is LC033, type is output.
shuzih1 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC056 & !_LC058 & _X003 & _X004 & _X005 & _X006;
_X003 = EXP(!down & !ld & shuzih1 & !shuzil0);
_X004 = EXP(!ld & shuzih1 & shuzil2);
_X005 = EXP(!ld & shuzih1 & shuzil1);
_X006 = EXP(!ld & shuzih1 & !start);
-- Node name is 'shuzih2' = '~225~1'
-- Equation name is 'shuzih2', location is LC035, type is output.
shuzih2 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC054 & !_LC055 & _X007 & _X008 & _X009 & _X010;
_X007 = EXP(!down & !ld & shuzih2 & !shuzil0);
_X008 = EXP(!ld & shuzih2 & shuzil2);
_X009 = EXP(!ld & shuzih2 & shuzil1);
_X010 = EXP(!ld & shuzih2 & !start);
-- Node name is 'shuzih3' = '~224~1'
-- Equation name is 'shuzih3', location is LC052, type is output.
shuzih3 = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC059 & !_LC061 & _X011 & _X012 & _X013 & _X014 & _X015;
_X011 = EXP(!ld & shuzih3 & shuzil0 & !up);
_X012 = EXP(!down & !ld & shuzih3 & !shuzil0);
_X013 = EXP(!ld & shuzih3 & shuzil1);
_X014 = EXP(!ld & shuzih3 & shuzil2);
_X015 = EXP(!ld & shuzih3 & !start);
-- Node name is 'shuzil0' = '~113~1'
-- Equation name is 'shuzil0', location is LC049, type is output.
shuzil0 = LCELL( _EQ006 $ _LC041);
_EQ006 = down & !_LC041 & !shuzil0 & !shuzil1 & !shuzil2 & !shuzil3 &
start
# !down & !_LC041 & !ld & shuzil0 & start & !up
# down & _LC018 & !_LC041 & start & !up
# _LC057;
-- Node name is 'shuzil1' = '~112~1'
-- Equation name is 'shuzil1', location is LC040, type is output.
shuzil1 = LCELL( _EQ007 $ GND);
_EQ007 = down & _LC047 & start & !up & _X016
# _LC034 & start & up & _X017
# !down & !ld & shuzil1 & !up
# !ld & shuzil1 & !start
# _LC046;
_X016 = EXP(!shuzil0 & !shuzil1 & !shuzil2 & !shuzil3);
_X017 = EXP( shuzil0 & !shuzil1 & !shuzil2 & shuzil3);
-- Node name is 'shuzil2' = '~111~1'
-- Equation name is 'shuzil2', location is LC037, type is output.
shuzil2 = LCELL( _EQ008 $ GND);
_EQ008 = down & _LC039 & start & !up & _X016
# _LC060 & start & up & _X017
# !down & !ld & shuzil2 & !up
# !ld & shuzil2 & !start
# _LC044;
_X016 = EXP(!shuzil0 & !shuzil1 & !shuzil2 & !shuzil3);
_X017 = EXP( shuzil0 & !shuzil1 & !shuzil2 & shuzil3);
-- Node name is 'shuzil3' = '~110~1'
-- Equation name is 'shuzil3', location is LC036, type is output.
shuzil3 = LCELL( _EQ009 $ GND);
_EQ009 = down & !shuzil0 & !shuzil1 & !shuzil2 & !shuzil3 & start & !up
# _LC064 & start & up & _X017
# down & _LC038 & start & !up
# !down & !ld & shuzil3 & !up
# _LC043;
_X017 = EXP( shuzil0 & !shuzil1 & !shuzil2 & shuzil3);
-- Node name is '|lpm_add_sub:228|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC034', type is buried
_LC034 = LCELL(!shuzil1 $ !shuzil0);
-- Node name is '|lpm_add_sub:228|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried
_LC060 = LCELL( shuzil2 $ _EQ010);
_EQ010 = shuzil0 & shuzil1;
-- Node name is '|lpm_add_sub:228|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC064', type is buried
_LC064 = LCELL( shuzil3 $ _EQ011);
_EQ011 = shuzil0 & shuzil1 & shuzil2;
-- Node name is '|lpm_add_sub:229|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC048', type is buried
_LC048 = LCELL( _EQ012 $ shuzil2);
_EQ012 = shuzil1 & !shuzil2;
-- Node name is '|lpm_add_sub:229|addcore:adder|addcore:adder0|pp0~1' from file "addcore.tdf" line 328, column 22
-- Equation name is '_LC018', type is buried
-- synthesized logic cell
_LC018 = LCELL(!shuzil0 $ GND);
-- Node name is '|lpm_add_sub:229|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried
_LC047 = LCELL(!shuzil1 $ !_LC018);
-- Node name is '|lpm_add_sub:229|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC039', type is buried
_LC039 = LCELL( _EQ013 $ shuzil2);
_EQ013 = _LC018 & !shuzil1;
-- Node name is '|lpm_add_sub:229|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC038', type is buried
_LC038 = LCELL( _EQ014 $ shuzil3);
_EQ014 = _LC018 & !_LC048;
-- Node name is '|lpm_add_sub:230|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
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