📄 jishuqi.rpt
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Project Information d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/28/2007 18:27:20
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
jishuqi EPM7064LC44-7 4 8 0 33 17 51 %
User Pins: 4 8 0
Project Information d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
** FILE HIERARCHY **
|lpm_add_sub:228|
|lpm_add_sub:228|addcore:adder|
|lpm_add_sub:228|addcore:adder|addcore:adder0|
|lpm_add_sub:228|altshift:result_ext_latency_ffs|
|lpm_add_sub:228|altshift:carry_ext_latency_ffs|
|lpm_add_sub:228|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:229|
|lpm_add_sub:229|addcore:adder|
|lpm_add_sub:229|addcore:adder|addcore:adder0|
|lpm_add_sub:229|altshift:result_ext_latency_ffs|
|lpm_add_sub:229|altshift:carry_ext_latency_ffs|
|lpm_add_sub:229|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:230|
|lpm_add_sub:230|addcore:adder|
|lpm_add_sub:230|addcore:adder|addcore:adder0|
|lpm_add_sub:230|altshift:result_ext_latency_ffs|
|lpm_add_sub:230|altshift:carry_ext_latency_ffs|
|lpm_add_sub:230|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:231|
|lpm_add_sub:231|addcore:adder|
|lpm_add_sub:231|addcore:adder|addcore:adder0|
|lpm_add_sub:231|altshift:result_ext_latency_ffs|
|lpm_add_sub:231|altshift:carry_ext_latency_ffs|
|lpm_add_sub:231|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
***** Logic for device 'jishuqi' compiled without errors.
Device: EPM7064LC44-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R R R R
E E E E E
S S S S S
E E E E E
R R R R R
V V V V G G G G G V V
E E E C N N N N N E E
D D D C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | RESERVED
start | 8 38 | RESERVED
up | 9 37 | RESERVED
GND | 10 36 | shuzih3
ld | 11 35 | VCC
down | 12 EPM7064LC44-7 34 | shuzih0
RESERVED | 13 33 | shuzil0
RESERVED | 14 32 | RESERVED
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V s s s s s
E E E E N C h h h h h
S S S S D C u u u u u
E E E E z z z z z
R R R R i i i i i
V V V V h h l l l
E E E E 1 2 3 2 1
D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 4/ 8( 50%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 1/16( 6%) 0/ 8( 0%) 0/16( 0%) 1/36( 2%)
C: LC33 - LC48 16/16(100%) 5/ 8( 62%) 16/16(100%) 26/36( 72%)
D: LC49 - LC64 16/16(100%) 3/ 8( 37%) 16/16(100%) 22/36( 61%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 12/32 ( 37%)
Total logic cells used: 33/64 ( 51%)
Total shareable expanders used: 17/64 ( 26%)
Total Turbo logic cells used: 33/64 ( 51%)
Total shareable expanders not available (n/a): 15/64 ( 23%)
Average fan-in: 7.24
Total fan-in: 239
Total input pins required: 4
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 33
Total flipflops required: 0
Total product terms required: 124
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 17
Synthesized logic cells: 23/ 64 ( 35%)
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
12 (1) (A) INPUT 0 0 0 0 0 8 10 down
11 (3) (A) INPUT 0 0 0 0 0 8 10 ld
8 (5) (A) INPUT 0 0 0 0 0 8 12 start
9 (4) (A) INPUT 0 0 0 0 0 6 12 up
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
34 51 D OUTPUT s t 3 0 1 4 10 1 9 shuzih0
24 33 C OUTPUT s t 4 0 0 3 6 2 7 shuzih1
25 35 C OUTPUT s t 4 0 0 3 6 2 7 shuzih2
36 52 D OUTPUT s t 5 0 0 4 6 2 6 shuzih3
33 49 D OUTPUT s t 1 0 1 4 7 8 16 shuzil0
28 40 C OUTPUT s t 3 2 1 4 7 8 15 shuzil1
27 37 C OUTPUT s t 3 2 1 4 7 8 14 shuzil2
26 36 C OUTPUT s t 2 1 1 4 7 5 13 shuzil3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 34 C SOFT t 0 0 0 0 2 1 1 |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node1
- 60 D SOFT t 0 0 0 0 3 1 1 |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node2
(41) 64 D SOFT t 0 0 0 0 4 1 1 |lpm_add_sub:228|addcore:adder|addcore:adder0|result_node3
(32) 48 C SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:229|addcore:adder|addcore:adder0|gcp2
- 18 B LCELL s t 0 0 0 0 1 1 4 |lpm_add_sub:229|addcore:adder|addcore:adder0|pp0~1
- 47 C SOFT t 0 0 0 0 2 1 1 |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node1
- 39 C SOFT t 0 0 0 0 3 1 1 |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node2
- 38 C SOFT t 0 0 0 0 3 1 2 |lpm_add_sub:229|addcore:adder|addcore:adder0|result_node3
- 63 D SOFT t 0 0 0 0 4 0 2 |lpm_add_sub:230|addcore:adder|addcore:adder0|result_node3
- 45 C SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:231|addcore:adder|addcore:adder0|gcp2
(37) 53 D LCELL s t 0 0 0 0 1 1 4 |lpm_add_sub:231|addcore:adder|addcore:adder0|pp0~1
- 50 D SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:231|addcore:adder|addcore:adder0|result_node3
(29) 41 C LCELL s t 0 0 0 2 1 1 1 ~109~1
- 42 C LCELL s t 2 1 1 4 6 0 1 ~110~1~2
- 43 C LCELL s t 0 0 0 4 3 1 0 ~110~1~3
- 44 C LCELL s t 3 2 1 4 6 1 0 ~111~1~2
(31) 46 C LCELL s t 3 2 1 4 6 1 0 ~112~1~2
(39) 57 D LCELL s t 0 0 0 4 3 1 0 ~113~1~2
- 59 D SOFT s t 1 0 1 3 10 1 0 ~224~2
- 61 D SOFT s t 1 0 1 3 8 1 0 ~224~3
- 54 D SOFT s t 1 0 1 3 9 1 0 ~225~2
- 55 D SOFT s t 1 0 1 3 7 1 0 ~225~3
(38) 56 D SOFT s t 1 0 1 3 9 1 0 ~226~2
- 58 D SOFT s t 1 0 1 4 7 1 0 ~226~3
(40) 62 D SOFT s t 1 0 1 3 4 1 0 ~227~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+- LC18 |lpm_add_sub:229|addcore:adder|addcore:adder0|pp0~1
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