jifen1.v

在FPGA上

module shuzi(
			clr,//置数输出10
			clk,
			enable,//使能,接第一组抢答信号
			up,//答对按钮
			down,//答错按钮
			shuzi);//得分输出位宽8位
input clr,clk,enable,up,down;
output [7:0] shuzi;

wire clr,clk,enable,up,down;
reg [7:0] shuzi;

reg [3:0]count_l;
reg [3:0]count_h;

always@( posedge clk  )//posedge clk or posedge load 
begin
	if(clr)//load
	begin
		count_l=0;
		count_h=1;
		shuzi[3:0]=count_l;
		shuzi[7:4]=count_h;
	end
	else
	begin
		if(enable&&up)
		begin
				if(count_l==9)
				begin		
					count_l=0;
					count_h=count_h+1;
					shuzi[3:0]=0;
					shuzi[7:4]=count_h;
				end
				else if(count_l<9&&count_h<=9)
				begin
					count_l=count_l+1;
					shuzi[3:0]=count_l;
					shuzi[7:4]=count_h;
				end
				else
				begin
					shuzi[3:0]=count_l;
					shuzi[7:4]=count_h;
				end	

		 end
		 if(enable&&down) 
			begin
				if(count_h>0&&count_l==0)
				begin		
					count_l=9;
					count_h=count_h-1;
					shuzi[3:0]=9;
					shuzi[7:4]=count_h;
				end
				else if(count_h==0&&count_l==0)
				begin 
					count_l=0;
					count_h=0;
					shuzi[3:0]=count_l;
					shuzi[7:4]=count_h;
				end

				else 
				begin
					count_l=count_l-1;
					shuzi[3:0]=count_l;
					shuzi[7:4]=count_h;
				end
				
			end	
			else
			begin
					shuzi[3:0]=count_l;
					shuzi[7:4]=count_h;

			end
		end
	end

	
endmodule