clk100_2.v

来自「在FPGA上」· Verilog 代码 · 共 37 行

module clk100_2(reset,clk_in,f1,f500);
input clk_in,reset;
output f1,f500;
reg f1,f500;
reg[9:0] c100,c2;
always @(posedge clk_in)
  begin 
   if(reset==1)
   begin
   c100<=0;
   f1<=0;
   end
   else if(c100==999)
   begin
   f1<=1;
   c100<=0;
   end
   else if(c100<999)
   begin 
   c100<=c100+1;
   f1<=0;
   end
   end
always @(posedge clk_in)
  begin 
   if(reset==1)
   begin
   f500<=0;
   c2<=0;
   end
   else
   f500<=~f500;
   
  end
endmodule