distans_count.v

来自「在FPGA上」· Verilog 代码 · 共 27 行

module	distans_count(start,reset,number,distansl,distansh);
input	start,reset,number;
output	distansl,distansh;
reg[3:0]	distansl,distansh;
wire	start,reset,number;	
always @(posedge number)
begin
if(reset)
begin
      {distansl,distansh}<=8'h00;      
end
else
if(start)
begin
if(distansl==9)  
                begin
                  distansl<=0;
                  if(distansh==9)
                    distansh<=0;
                  else distansh<=distansh+1;
                end
else distansl<=distansl+1;
end
end
endmodule