count3.v

来自「在FPGA上」· Verilog 代码 · 共 27 行

module count3(out,reset,clk_in);
input clk_in,reset;
output out;
reg out;
reg[1:0] c3;


always @(posedge clk_in)
  begin 
   if(!reset) 
   begin
   c3=0;
   out=0;
   end 
 else if(c3==2)
   begin
   out=1;
   c3=0;
   end
 else if(c3<2)
   begin 
   c3=c3+1;
   out=0;
   end
 end
endmodule