📄 shuzi.rpt
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# !_LC8_B24;
-- Node name is ':136'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ022);
_EQ022 = _LC3_B21 & _LC6_B21
# _LC3_B17 & _LC6_B21
# !_LC3_B17 & !_LC3_B21 & _LC6_B16 & !_LC6_B21
# !_LC6_B16 & _LC6_B21;
-- Node name is ':138'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = LCELL( _EQ023);
_EQ023 = _LC2_B17 & _LC5_B17
# !_LC2_B17 & !_LC5_B17 & _LC6_B16
# _LC5_B17 & !_LC6_B16;
-- Node name is ':150'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ024);
_EQ024 = _LC3_B17 & _LC3_B21
# !_LC3_B17 & !_LC3_B21 & _LC4_B13 & _LC6_B16
# _LC3_B21 & !_LC6_B16
# _LC3_B21 & !_LC4_B13;
-- Node name is ':192'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ025);
_EQ025 = !count_h3 & _LC5_B14
# !count_h1 & !count_h2 & _LC5_B14;
-- Node name is ':202'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ026);
_EQ026 = !count_l2 & count_l3
# count_l3 & !_LC2_B14
# count_l2 & !count_l3 & _LC2_B14 & _LC2_B21
# count_l3 & !_LC2_B21;
-- Node name is ':203'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = LCELL( _EQ027);
_EQ027 = !count_l1 & count_l2
# !count_l0 & count_l2
# count_l0 & count_l1 & !count_l2 & _LC2_B21
# count_l2 & !_LC2_B21;
-- Node name is ':204'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ028);
_EQ028 = !count_l0 & count_l1
# count_l0 & !count_l1 & _LC2_B21
# count_l1 & !_LC2_B21;
-- Node name is ':223'
-- Equation name is '_LC4_B14', type is buried
_LC4_B14 = LCELL( _EQ029);
_EQ029 = _LC2_B13 & _LC6_B14 & !_LC8_B14
# count_l3 & !_LC2_B13;
-- Node name is ':224'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ030);
_EQ030 = _LC2_B13 & _LC7_B16 & !_LC8_B14
# count_l2 & !_LC2_B13;
-- Node name is ':225'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ031);
_EQ031 = _LC1_B14 & _LC2_B13 & !_LC8_B14
# count_l1 & !_LC2_B13;
-- Node name is ':226'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ032);
_EQ032 = count_l0 & !_LC2_B21 & !_LC8_B14
# !count_l0 & _LC2_B13 & _LC2_B21 & !_LC8_B14
# count_l0 & !_LC2_B13;
-- Node name is ':247'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ033);
_EQ033 = !_LC4_B14 & _LC7_B21 & !_LC7_B24
# !_LC4_B14 & _LC6_B21 & !_LC7_B24
# _LC4_B14 & _LC7_B24;
-- Node name is '~252~1'
-- Equation name is '~252~1', location is LC4_B24, type is buried.
-- synthesized logic cell
_LC4_B24 = LCELL( _EQ034);
_EQ034 = _LC4_B13 & !_LC8_B24;
-- Node name is ':252'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ035);
_EQ035 = _LC3_B14 & _LC4_B16 & _LC4_B24
# _LC1_B16 & _LC4_B16 & _LC4_B24
# !_LC1_B16 & !_LC3_B14 & !_LC4_B16 & _LC4_B24;
-- Node name is ':262'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ036);
_EQ036 = _LC1_B16 & _LC3_B14 & _LC4_B24
# !_LC1_B16 & !_LC3_B14 & _LC4_B24
# _LC3_B14 & !_LC4_B13;
-- Node name is ':263'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ037);
_EQ037 = _LC4_B13 & _LC5_B16 & _LC8_B24
# !_LC1_B16 & _LC4_B13 & !_LC8_B24
# !_LC1_B16 & _LC4_B13 & _LC5_B16
# _LC1_B16 & !_LC4_B13;
-- Node name is ':298'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ038);
_EQ038 = count_h3 & !_LC8_B13
# !count_h2 & count_h3
# count_h3 & !_LC1_B15
# count_h2 & !count_h3 & _LC1_B15 & _LC8_B13;
-- Node name is ':299'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ039);
_EQ039 = !count_h1 & count_h2
# !count_h0 & count_h2
# count_h2 & !_LC8_B13
# count_h0 & count_h1 & !count_h2 & _LC8_B13;
-- Node name is ':300'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = LCELL( _EQ040);
_EQ040 = !count_h0 & count_h1
# count_h1 & !_LC8_B13
# count_h0 & !count_h1 & _LC8_B13;
-- Node name is ':301'
-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = LCELL( _EQ041);
_EQ041 = count_h0 & !_LC8_B14
# !count_h0 & _LC2_B13 & _LC8_B14
# count_h0 & !_LC2_B13;
-- Node name is ':545'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = DFFE( _EQ042, GLOBAL( clk), VCC, VCC, VCC);
_EQ042 = !clr & _LC4_B13 & _LC5_B21
# !clr & !_LC4_B13 & _LC6_B21;
-- Node name is ':546'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = DFFE( _EQ043, GLOBAL( clk), VCC, VCC, VCC);
_EQ043 = !clr & _LC4_B21;
-- Node name is ':547'
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = DFFE( _EQ044, GLOBAL( clk), VCC, VCC, VCC);
_EQ044 = !clr & _LC4_B13 & _LC7_B17
# !clr & !_LC4_B13 & _LC5_B17;
-- Node name is ':548'
-- Equation name is '_LC8_B17', type is buried
_LC8_B17 = DFFE( _EQ045, GLOBAL( clk), VCC, VCC, VCC);
_EQ045 = _LC2_B17 & !_LC6_B16
# !_LC2_B17 & _LC4_B13 & _LC6_B16
# _LC2_B17 & !_LC4_B13
# clr;
-- Node name is ':549'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE( _EQ046, GLOBAL( clk), VCC, VCC, VCC);
_EQ046 = !clr & _LC1_B24 & _LC4_B13
# !clr & !_LC4_B13 & _LC4_B14;
-- Node name is ':550'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = DFFE( _EQ047, GLOBAL( clk), VCC, VCC, VCC);
_EQ047 = !clr & !_LC4_B13 & _LC4_B16
# !clr & _LC5_B24;
-- Node name is ':551'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = DFFE( _EQ048, GLOBAL( clk), VCC, VCC, VCC);
_EQ048 = !clr & _LC6_B24;
-- Node name is ':552'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = DFFE( _EQ049, GLOBAL( clk), VCC, VCC, VCC);
_EQ049 = !clr & _LC8_B16;
Project Information d:\tools\altera.max.plus.ii\wodeshji\shuzi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,081K
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