📄 shuzi.rpt
字号:
- 4 - B 13 OR2 ! 2 0 0 14 :31
- 8 - B 13 AND2 s 0 2 0 3 ~32~1
- 2 - B 13 OR2 ! 2 0 0 6 :32
- 5 - B 16 OR2 0 2 0 1 :44
- 8 - B 14 OR2 ! 0 4 0 6 :61
- 5 - B 14 OR2 0 4 0 1 :79
- 8 - B 24 OR2 s ! 0 4 0 3 ~103~1
- 6 - B 16 OR2 ! 0 3 0 5 :103
- 5 - B 21 OR2 0 4 0 2 :136
- 7 - B 17 OR2 0 3 0 2 :138
- 4 - B 21 OR2 0 4 0 2 :150
- 8 - B 21 DFFE + 1 3 0 2 count_h3 (:161)
- 3 - B 13 DFFE + 1 1 0 3 count_h2 (:162)
- 6 - B 17 DFFE + 1 3 0 4 count_h1 (:163)
- 1 - B 17 DFFE + 1 3 0 4 count_h0 (:164)
- 2 - B 21 OR2 0 4 0 4 :192
- 6 - B 14 OR2 0 4 0 1 :202
- 7 - B 16 OR2 0 4 0 1 :203
- 1 - B 14 OR2 0 3 0 1 :204
- 4 - B 14 OR2 0 4 0 4 :223
- 4 - B 16 OR2 0 4 0 5 :224
- 3 - B 14 OR2 0 4 0 4 :225
- 1 - B 16 OR2 0 4 0 5 :226
- 1 - B 24 OR2 0 4 0 2 :247
- 4 - B 24 AND2 s 0 2 0 2 ~252~1
- 5 - B 24 OR2 0 4 0 2 :252
- 6 - B 24 OR2 0 4 0 2 :262
- 8 - B 16 OR2 0 4 0 2 :263
- 7 - B 14 DFFE + 1 3 0 4 count_l3 (:272)
- 3 - B 24 DFFE + 1 3 0 5 count_l2 (:273)
- 6 - B 13 DFFE + 1 1 0 6 count_l1 (:274)
- 3 - B 16 DFFE + 1 1 0 6 count_l0 (:275)
- 6 - B 21 OR2 0 4 0 6 :298
- 3 - B 21 OR2 0 4 0 3 :299
- 5 - B 17 OR2 0 3 0 4 :300
- 2 - B 17 OR2 0 3 0 4 :301
- 1 - B 21 DFFE + 1 3 1 0 :545
- 7 - B 13 DFFE + 1 1 1 0 :546
- 4 - B 17 DFFE + 1 3 1 0 :547
- 8 - B 17 DFFE + 1 3 1 0 :548
- 1 - B 13 DFFE + 1 3 1 0 :549
- 2 - B 24 DFFE + 1 3 1 0 :550
- 5 - B 13 DFFE + 1 1 1 0 :551
- 2 - B 16 DFFE + 1 1 1 0 :552
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\shuzi.rpt
shuzi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 29/ 48( 60%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\shuzi.rpt
shuzi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\shuzi.rpt
shuzi
** EQUATIONS **
clk : INPUT;
clr : INPUT;
down : INPUT;
enable : INPUT;
up : INPUT;
-- Node name is ':164' = 'count_h0'
-- Equation name is 'count_h0', location is LC1_B17, type is buried.
count_h0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = clr
# _LC2_B17 & !_LC6_B16
# !_LC2_B17 & _LC4_B13 & _LC6_B16
# _LC2_B17 & !_LC4_B13;
-- Node name is ':163' = 'count_h1'
-- Equation name is 'count_h1', location is LC6_B17, type is buried.
count_h1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !clr & _LC4_B13 & _LC7_B17
# !clr & !_LC4_B13 & _LC5_B17;
-- Node name is ':162' = 'count_h2'
-- Equation name is 'count_h2', location is LC3_B13, type is buried.
count_h2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !clr & _LC4_B21;
-- Node name is ':161' = 'count_h3'
-- Equation name is 'count_h3', location is LC8_B21, type is buried.
count_h3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !clr & _LC4_B13 & _LC5_B21
# !clr & !_LC4_B13 & _LC6_B21;
-- Node name is ':275' = 'count_l0'
-- Equation name is 'count_l0', location is LC3_B16, type is buried.
count_l0 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !clr & _LC8_B16;
-- Node name is ':274' = 'count_l1'
-- Equation name is 'count_l1', location is LC6_B13, type is buried.
count_l1 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !clr & _LC6_B24;
-- Node name is ':273' = 'count_l2'
-- Equation name is 'count_l2', location is LC3_B24, type is buried.
count_l2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !clr & _LC5_B24
# !clr & !_LC4_B13 & _LC4_B16;
-- Node name is ':272' = 'count_l3'
-- Equation name is 'count_l3', location is LC7_B14, type is buried.
count_l3 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !clr & _LC1_B24 & _LC4_B13
# !clr & !_LC4_B13 & _LC4_B14;
-- Node name is 'shuzi0'
-- Equation name is 'shuzi0', type is output
shuzi0 = _LC2_B16;
-- Node name is 'shuzi1'
-- Equation name is 'shuzi1', type is output
shuzi1 = _LC5_B13;
-- Node name is 'shuzi2'
-- Equation name is 'shuzi2', type is output
shuzi2 = _LC2_B24;
-- Node name is 'shuzi3'
-- Equation name is 'shuzi3', type is output
shuzi3 = _LC1_B13;
-- Node name is 'shuzi4'
-- Equation name is 'shuzi4', type is output
shuzi4 = _LC8_B17;
-- Node name is 'shuzi5'
-- Equation name is 'shuzi5', type is output
shuzi5 = _LC4_B17;
-- Node name is 'shuzi6'
-- Equation name is 'shuzi6', type is output
shuzi6 = _LC7_B13;
-- Node name is 'shuzi7'
-- Equation name is 'shuzi7', type is output
shuzi7 = _LC1_B21;
-- Node name is '|lpm_add_sub:553|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ009);
_EQ009 = _LC2_B17
# _LC5_B17;
-- Node name is '|lpm_add_sub:553|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = LCELL( _EQ010);
_EQ010 = _LC3_B21
# _LC3_B17;
-- Node name is '|lpm_add_sub:554|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = LCELL( _EQ011);
_EQ011 = count_l0 & count_l1;
-- Node name is '|lpm_add_sub:555|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = LCELL( _EQ012);
_EQ012 = _LC3_B14
# _LC1_B16
# _LC4_B16;
-- Node name is '|lpm_add_sub:556|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B15', type is buried
_LC1_B15 = LCELL( _EQ013);
_EQ013 = count_h0 & count_h1;
-- Node name is ':31'
-- Equation name is '_LC4_B13', type is buried
!_LC4_B13 = _LC4_B13~NOT;
_LC4_B13~NOT = LCELL( _EQ014);
_EQ014 = !enable
# !down;
-- Node name is '~32~1'
-- Equation name is '~32~1', location is LC8_B13, type is buried.
-- synthesized logic cell
_LC8_B13 = LCELL( _EQ015);
_EQ015 = _LC2_B13 & _LC8_B14;
-- Node name is ':32'
-- Equation name is '_LC2_B13', type is buried
!_LC2_B13 = _LC2_B13~NOT;
_LC2_B13~NOT = LCELL( _EQ016);
_EQ016 = !enable
# !up;
-- Node name is ':44'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ017);
_EQ017 = _LC7_B21
# _LC6_B21;
-- Node name is ':61'
-- Equation name is '_LC8_B14', type is buried
!_LC8_B14 = _LC8_B14~NOT;
_LC8_B14~NOT = LCELL( _EQ018);
_EQ018 = !count_l0
# !count_l3
# count_l2
# count_l1;
-- Node name is ':79'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ019);
_EQ019 = !count_l3
# !count_l0 & !count_l1 & !count_l2;
-- Node name is '~103~1'
-- Equation name is '~103~1', location is LC8_B24, type is buried.
-- synthesized logic cell
!_LC8_B24 = _LC8_B24~NOT;
_LC8_B24~NOT = LCELL( _EQ020);
_EQ020 = _LC4_B16
# _LC3_B14
# _LC1_B16
# _LC4_B14;
-- Node name is ':103'
-- Equation name is '_LC6_B16', type is buried
!_LC6_B16 = _LC6_B16~NOT;
_LC6_B16~NOT = LCELL( _EQ021);
_EQ021 = !_LC6_B21 & !_LC7_B21
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -