📄 clk100_2.rpt
字号:
| | | | | | | | +--------------- LC28 c1007
| | | | | | | | | +------------- LC27 c1006
| | | | | | | | | | +----------- LC26 c1005
| | | | | | | | | | | +--------- LC20 c1004
| | | | | | | | | | | | +------- LC19 c1003
| | | | | | | | | | | | | +----- LC18 c1002
| | | | | | | | | | | | | | +--- LC17 c1001
| | | | | | | | | | | | | | | +- LC21 c1000
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC24 -> - - - - - - - - - - * - - - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder0|result_node5
LC23 -> - - - - - - - - - * - - - - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder0|result_node6
LC22 -> - - - - - - - - * - - - - - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder0|result_node7
LC32 -> - - - - - - - * - - - - - - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder1|result_node0
LC31 -> - - - - - - * - - - - - - - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder1|result_node1
LC30 -> * - - - - * * * * * * * * * * * | - * | <-- c1009
LC29 -> * - - - * * * * * * * * * * * * | - * | <-- c1008
LC28 -> * - - * * * * * * * * * * * * * | - * | <-- c1007
LC27 -> * - * * * * * * * * * * * * * * | - * | <-- c1006
LC26 -> * * * * * * * * * * * * * * * * | - * | <-- c1005
LC20 -> * * * * * * * * * * * * * * * * | * * | <-- c1004
LC19 -> * * * * * * * * * * * * * * * * | * * | <-- c1003
LC18 -> * * * * * * * * * * * * * * - - | * * | <-- c1002
LC17 -> * * * * * * * * * * * * * * * - | * * | <-- c1001
LC21 -> * * * * * * * * * * * * * * * * | * * | <-- c1000
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk_in
4 -> * - - - - - * * * * * * * * * * | * * | <-- reset
LC4 -> - - - - - - - - - - - - - * - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder0|result_node2
LC8 -> - - - - - - - - - - - - * - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder0|result_node3
LC12 -> - - - - - - - - - - - * - - - - | - * | <-- |lpm_add_sub:174|addcore:adder|addcore:adder0|result_node4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\tools\altera.max.plus.ii\wodeshji\clk100_2.rpt
clk100_2
** EQUATIONS **
clk_in : INPUT;
reset : INPUT;
-- Node name is ':155' = 'c1000'
-- Equation name is 'c1000', location is LC021, type is buried.
c1000 = DFFE( _EQ001 $ !reset, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ001 = c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & !reset
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & !reset
# c1000 & !reset;
-- Node name is ':154' = 'c1001'
-- Equation name is 'c1001', location is LC017, type is buried.
c1001 = DFFE( _EQ002 $ !reset, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ002 = c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & !reset
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & !reset
# c1000 & c1001 & !reset
# !c1000 & !c1001 & !reset;
-- Node name is ':153' = 'c1002'
-- Equation name is 'c1002', location is LC018, type is buried.
c1002 = DFFE( _EQ003 $ _LC004, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ003 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC004
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC004
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC004
# _LC004 & reset;
-- Node name is ':152' = 'c1003'
-- Equation name is 'c1003', location is LC019, type is buried.
c1003 = DFFE( _EQ004 $ _LC008, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ004 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC008
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC008
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC008
# _LC008 & reset;
-- Node name is ':151' = 'c1004'
-- Equation name is 'c1004', location is LC020, type is buried.
c1004 = DFFE( _EQ005 $ _LC012, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ005 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC012
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC012
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC012
# _LC012 & reset;
-- Node name is ':150' = 'c1005'
-- Equation name is 'c1005', location is LC026, type is buried.
c1005 = DFFE( _EQ006 $ _LC024, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ006 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC024
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC024
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC024
# _LC024 & reset;
-- Node name is ':149' = 'c1006'
-- Equation name is 'c1006', location is LC027, type is buried.
c1006 = DFFE( _EQ007 $ _LC023, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ007 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC023
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC023
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC023
# _LC023 & reset;
-- Node name is ':148' = 'c1007'
-- Equation name is 'c1007', location is LC028, type is buried.
c1007 = DFFE( _EQ008 $ _LC022, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ008 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC022
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC022
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC022
# _LC022 & reset;
-- Node name is ':147' = 'c1008'
-- Equation name is 'c1008', location is LC029, type is buried.
c1008 = DFFE( _EQ009 $ _LC032, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ009 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC032
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC032
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC032
# _LC032 & reset;
-- Node name is ':146' = 'c1009'
-- Equation name is 'c1009', location is LC030, type is buried.
c1009 = DFFE( _EQ010 $ _LC031, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ010 = c1000 & c1001 & c1002 & c1005 & c1006 & c1007 & c1008 &
c1009 & _LC031
# c1003 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC031
# c1004 & c1005 & c1006 & c1007 & c1008 & c1009 & _LC031
# _LC031 & reset;
-- Node name is 'f1' = ':164'
-- Equation name is 'f1', type is output
f1 = DFFE( _EQ011 $ GND, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ011 = c1000 & c1001 & c1002 & !c1003 & !c1004 & c1005 & c1006 &
c1007 & c1008 & c1009 & !reset;
-- Node name is 'f500' = ':173'
-- Equation name is 'f500', type is output
f500 = DFFE( _EQ012 $ !reset, GLOBAL( clk_in), VCC, VCC, VCC);
_EQ012 = f500 & !reset;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( c1002 $ _EQ013);
_EQ013 = c1000 & c1001;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( c1003 $ _EQ014);
_EQ014 = c1000 & c1001 & c1002;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried
_LC012 = LCELL( c1004 $ _EQ015);
_EQ015 = c1000 & c1001 & c1002 & c1003;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( c1005 $ _EQ016);
_EQ016 = c1000 & c1001 & c1002 & c1003 & c1004;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( c1006 $ _EQ017);
_EQ017 = c1000 & c1001 & c1002 & c1003 & c1004 & c1005;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( c1007 $ _EQ018);
_EQ018 = c1000 & c1001 & c1002 & c1003 & c1004 & c1005 & c1006;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( c1008 $ _EQ019);
_EQ019 = c1000 & c1001 & c1002 & c1003 & c1004 & c1005 & c1006 &
c1007;
-- Node name is '|lpm_add_sub:174|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( c1009 $ _EQ020);
_EQ020 = c1000 & c1001 & c1002 & c1003 & c1004 & c1005 & c1006 &
c1007 & c1008;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\tools\altera.max.plus.ii\wodeshji\clk100_2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,115K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -