📄 de2_nios.fit.rpt
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; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Always Enable Input Buffers ; Off ; Off ;
+------------------------------------------------+--------------------------------+--------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations ;
+-----------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node ; Action ; Operation ; Reason ; Node Port ; Destination Node ; Destination Port ;
+-----------------------------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; I2C_AV_Config:u1|I2C_Controller:u0|SD[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[15] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[14] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[13] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[12] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[11] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[10] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[9] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[8] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[7] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[9] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[6] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[10] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[5] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[11] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[4] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[12] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[3] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[13] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[2] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[14] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[1] ; PORTADATAOUT ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[15] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_jgv:auto_generated|q_a[0] ; PORTADATAOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[0] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[0]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[1] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[1]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[2] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[2]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[3] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[3]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[4] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[4]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[5] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[5]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[6] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[6]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[7] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[7]~_Duplicate_1 ; REGOUT ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[8] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|mac_mult2 ; DATAA ;
; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[8] ; Duplicated ; Register Packing ; Timing optimization ; REGOUT ; system_0:u0|cpu_0:the_cpu_0|A_mul_src1[8]~_Duplicate_1 ; REGOUT ;
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