📄 switch_pio.v
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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
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//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
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//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 17: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 17: 0] in_port;
input reset_n;
wire clk_en;
wire [ 17: 0] data_in;
wire [ 17: 0] read_mux_out;
reg [ 17: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign data_in = in_port;
endmodule
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