📄 clock_0.v
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//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
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//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_master_read_done_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (1)
data_out <= data_in_d1;
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_master_write_done_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (1)
data_out <= data_in_d1;
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_edge_to_pulse (
// inputs:
clock,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clock;
input data_in;
input reset_n;
reg data_in_d1;
wire data_out;
always @(posedge clock or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
assign data_out = data_in ^ data_in_d1;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_slave_FSM (
// inputs:
master_read_done_token,
master_write_done_token,
slave_clk,
slave_read,
slave_reset_n,
slave_write,
// outputs:
slave_read_request,
slave_waitrequest,
slave_write_request
)
;
output slave_read_request;
output slave_waitrequest;
output slave_write_request;
input master_read_done_token;
input master_write_done_token;
input slave_clk;
input slave_read;
input slave_reset_n;
input slave_write;
reg next_slave_read_request;
reg [ 2: 0] next_slave_state;
reg next_slave_write_request;
reg slave_read_request;
reg [ 2: 0] slave_state;
reg slave_waitrequest;
reg slave_write_request;
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_read_request <= 0;
else if (1)
slave_read_request <= next_slave_read_request;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_write_request <= 0;
else if (1)
slave_write_request <= next_slave_write_request;
end
always @(posedge slave_clk or negedge slave_reset_n)
begin
if (slave_reset_n == 0)
slave_state <= 3'b001;
else if (1)
slave_state <= next_slave_state;
end
always @(master_read_done_token or master_write_done_token or slave_read or slave_read_request or slave_state or slave_write or slave_write_request)
begin
case (slave_state) // synthesis parallel_case
3'b001: begin
//read request: go from IDLE state to READ_WAIT state
if (slave_read)
begin
next_slave_state <= 3'b010;
slave_waitrequest <= 1;
next_slave_read_request <= !slave_read_request;
next_slave_write_request <= slave_write_request;
end
else if (slave_write)
begin
next_slave_state <= 3'b100;
slave_waitrequest <= 1;
next_slave_read_request <= slave_read_request;
next_slave_write_request <= !slave_write_request;
end
else
begin
next_slave_state <= slave_state;
slave_waitrequest <= 0;
next_slave_read_request <= slave_read_request;
next_slave_write_request <= slave_write_request;
end
end // 3'b001
3'b010: begin
//stay in READ_WAIT state until master passes read done token
if (master_read_done_token)
begin
next_slave_state <= 3'b001;
slave_waitrequest <= 0;
end
else
begin
next_slave_state <= 3'b010;
slave_waitrequest <= 1;
end
next_slave_read_request <= slave_read_request;
next_slave_write_request <= slave_write_request;
end // 3'b010
3'b100: begin
//stay in WRITE_WAIT state until master passes write done token
if (master_write_done_token)
begin
next_slave_state <= 3'b001;
slave_waitrequest <= 0;
end
else
begin
next_slave_state <= 3'b100;
slave_waitrequest <= 1;
end
next_slave_read_request <= slave_read_request;
next_slave_write_request <= slave_write_request;
end // 3'b100
default: begin
next_slave_state <= 3'b001;
slave_waitrequest <= 0;
next_slave_read_request <= slave_read_request;
next_slave_write_request <= slave_write_request;
end // default
endcase // slave_state
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_slave_read_request_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (1)
data_out <= data_in_d1;
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_slave_write_request_sync_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (1)
data_out <= data_in_d1;
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clock_0_master_FSM (
// inputs:
master_clk,
master_reset_n,
master_waitrequest,
slave_read_request_token,
slave_write_request_token,
// outputs:
master_read,
master_read_done,
master_write,
master_write_done
)
;
output master_read;
output master_read_done;
output master_write;
output master_write_done;
input master_clk;
input master_reset_n;
input master_waitrequest;
input slave_read_request_token;
input slave_write_request_token;
reg master_read;
reg master_read_done;
reg [ 2: 0] master_state;
reg master_write;
reg master_write_done;
reg next_master_read;
reg next_master_read_done;
reg [ 2: 0] next_master_state;
reg next_master_write;
reg next_master_write_done;
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_read_done <= 0;
else if (1)
master_read_done <= next_master_read_done;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_write_done <= 0;
else if (1)
master_write_done <= next_master_write_done;
end
always @(posedge master_clk or negedge master_reset_n)
begin
if (master_reset_n == 0)
master_read <= 0;
else if (1)
master_read <= next_master_read;
end
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