de2_nios.tan.summary

DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 9.869 ns
From           : SRAM_DQ[2]
To             : system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[18]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.008 ns
From           : system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|SEL_Cont[3]
To             : AUD_DACDAT
From Clock     : CLOCK_27
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.612 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.897 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 1.813 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 122.14 MHz ( period = 8.187 ns )
From           : system_0:u0|cpu_0:the_cpu_0|ic_fill_tag[4]
To             : system_0:u0|cpu_0:the_cpu_0|i_readdata_d1[2]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk2'
Slack          : 2.341 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|mCursor_X[2]
To             : system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|Cur_Color_R[6]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 9.283 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 93.31 MHz ( period = 10.717 ns )
From           : system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address
To             : system_0:u0|sdram_0:the_sdram_0|m_addr[2]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'Audio_PLL:PLL2|altpll:altpll_component|_clk0'
Slack          : 47.899 ns
Required Time  : 18.41 MHz ( period = 54.320 ns )
Actual Time    : 155.74 MHz ( period = 6.421 ns )
From           : system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|mDATA_RD
To             : system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|FIFO_16_256:u0|dcfifo:dcfifo_component|dcfifo_e6c1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8]
From Clock     : Audio_PLL:PLL2|altpll:altpll_component|_clk0
To Clock       : Audio_PLL:PLL2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 126.79 MHz ( period = 7.887 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[10]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 0.391 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : system_0:u0|SD_CLK:the_SD_CLK|data_out
To             : system_0:u0|SD_CLK:the_SD_CLK|data_out
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk2'
Slack          : 0.391 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|oVGA_V_SYNC
To             : system_0:u0|VGA_0:the_VGA_0|VGA_NIOS_CTRL:the_VGA_NIOS_CTRL|VGA_Controller:u0|oVGA_V_SYNC
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk2
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Clock Hold: 'Audio_PLL:PLL2|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 18.41 MHz ( period = 54.320 ns )
Actual Time    : N/A
From           : system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|LRCK_1X
To             : system_0:u0|Audio_0:the_Audio_0|AUDIO_DAC_FIFO:the_AUDIO_DAC_FIFO|LRCK_1X
From Clock     : Audio_PLL:PLL2|altpll:altpll_component|_clk0
To Clock       : Audio_PLL:PLL2|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : system_0:u0|sdram_0:the_sdram_0|i_cmd[3]
To             : system_0:u0|sdram_0:the_sdram_0|i_cmd[3]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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