📄 system_0.v
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endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ISP1362_avalon_slave_0_arbitrator (
// inputs:
ISP1362_avalon_slave_0_irq_n,
ISP1362_avalon_slave_0_readdata,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
ISP1362_avalon_slave_0_address,
ISP1362_avalon_slave_0_chipselect_n,
ISP1362_avalon_slave_0_irq_n_from_sa,
ISP1362_avalon_slave_0_read_n,
ISP1362_avalon_slave_0_readdata_from_sa,
ISP1362_avalon_slave_0_reset_n,
ISP1362_avalon_slave_0_wait_counter_eq_0,
ISP1362_avalon_slave_0_wait_counter_eq_1,
ISP1362_avalon_slave_0_write_n,
ISP1362_avalon_slave_0_writedata,
cpu_0_data_master_granted_ISP1362_avalon_slave_0,
cpu_0_data_master_qualified_request_ISP1362_avalon_slave_0,
cpu_0_data_master_read_data_valid_ISP1362_avalon_slave_0,
cpu_0_data_master_requests_ISP1362_avalon_slave_0,
d1_ISP1362_avalon_slave_0_end_xfer
)
/* synthesis auto_dissolve = "FALSE" */ ;
output [ 1: 0] ISP1362_avalon_slave_0_address;
output ISP1362_avalon_slave_0_chipselect_n;
output ISP1362_avalon_slave_0_irq_n_from_sa;
output ISP1362_avalon_slave_0_read_n;
output [ 15: 0] ISP1362_avalon_slave_0_readdata_from_sa;
output ISP1362_avalon_slave_0_reset_n;
output ISP1362_avalon_slave_0_wait_counter_eq_0;
output ISP1362_avalon_slave_0_wait_counter_eq_1;
output ISP1362_avalon_slave_0_write_n;
output [ 15: 0] ISP1362_avalon_slave_0_writedata;
output cpu_0_data_master_granted_ISP1362_avalon_slave_0;
output cpu_0_data_master_qualified_request_ISP1362_avalon_slave_0;
output cpu_0_data_master_read_data_valid_ISP1362_avalon_slave_0;
output cpu_0_data_master_requests_ISP1362_avalon_slave_0;
output d1_ISP1362_avalon_slave_0_end_xfer;
input ISP1362_avalon_slave_0_irq_n;
input [ 15: 0] ISP1362_avalon_slave_0_readdata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire [ 1: 0] ISP1362_avalon_slave_0_address;
wire ISP1362_avalon_slave_0_allgrants;
wire ISP1362_avalon_slave_0_allow_new_arb_cycle;
wire ISP1362_avalon_slave_0_any_continuerequest;
wire ISP1362_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] ISP1362_avalon_slave_0_arb_share_counter;
wire [ 2: 0] ISP1362_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] ISP1362_avalon_slave_0_arb_share_set_values;
wire ISP1362_avalon_slave_0_beginbursttransfer_internal;
wire ISP1362_avalon_slave_0_begins_xfer;
wire ISP1362_avalon_slave_0_chipselect_n;
wire [ 4: 0] ISP1362_avalon_slave_0_counter_load_value;
wire ISP1362_avalon_slave_0_end_xfer;
wire ISP1362_avalon_slave_0_firsttransfer;
wire ISP1362_avalon_slave_0_grant_vector;
wire ISP1362_avalon_slave_0_in_a_read_cycle;
wire ISP1362_avalon_slave_0_in_a_write_cycle;
wire ISP1362_avalon_slave_0_irq_n_from_sa;
wire ISP1362_avalon_slave_0_master_qreq_vector;
wire ISP1362_avalon_slave_0_non_bursting_master_requests;
wire ISP1362_avalon_slave_0_read_n;
wire [ 15: 0] ISP1362_avalon_slave_0_readdata_from_sa;
wire ISP1362_avalon_slave_0_reset_n;
reg ISP1362_avalon_slave_0_slavearbiterlockenable;
wire ISP1362_avalon_slave_0_slavearbiterlockenable2;
reg [ 4: 0] ISP1362_avalon_slave_0_wait_counter;
wire ISP1362_avalon_slave_0_wait_counter_eq_0;
wire ISP1362_avalon_slave_0_wait_counter_eq_1;
wire ISP1362_avalon_slave_0_waits_for_read;
wire ISP1362_avalon_slave_0_waits_for_write;
wire ISP1362_avalon_slave_0_write_n;
wire [ 15: 0] ISP1362_avalon_slave_0_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_ISP1362_avalon_slave_0;
wire cpu_0_data_master_qualified_request_ISP1362_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_ISP1362_avalon_slave_0;
wire cpu_0_data_master_requests_ISP1362_avalon_slave_0;
wire cpu_0_data_master_saved_grant_ISP1362_avalon_slave_0;
reg d1_ISP1362_avalon_slave_0_end_xfer;
reg d1_reasons_to_wait;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire wait_for_ISP1362_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else if (1)
d1_reasons_to_wait <= ~ISP1362_avalon_slave_0_end_xfer;
end
assign ISP1362_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_ISP1362_avalon_slave_0));
//assign ISP1362_avalon_slave_0_readdata_from_sa = ISP1362_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign ISP1362_avalon_slave_0_readdata_from_sa = ISP1362_avalon_slave_0_readdata;
assign cpu_0_data_master_requests_ISP1362_avalon_slave_0 = ({cpu_0_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h6810b0) & (cpu_0_data_master_read | cpu_0_data_master_write);
//ISP1362_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign ISP1362_avalon_slave_0_arb_share_set_values = 1;
//ISP1362_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign ISP1362_avalon_slave_0_non_bursting_master_requests = cpu_0_data_master_requests_ISP1362_avalon_slave_0;
//ISP1362_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign ISP1362_avalon_slave_0_arb_share_counter_next_value = ISP1362_avalon_slave_0_firsttransfer ? (ISP1362_avalon_slave_0_arb_share_set_values - 1) : |ISP1362_avalon_slave_0_arb_share_counter ? (ISP1362_avalon_slave_0_arb_share_counter - 1) : 0;
//ISP1362_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign ISP1362_avalon_slave_0_allgrants = |ISP1362_avalon_slave_0_grant_vector;
//ISP1362_avalon_slave_0_end_xfer assignment, which is an e_assign
assign ISP1362_avalon_slave_0_end_xfer = ~(ISP1362_avalon_slave_0_waits_for_read | ISP1362_avalon_slave_0_waits_for_write);
//ISP1362_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign ISP1362_avalon_slave_0_arb_counter_enable = (ISP1362_avalon_slave_0_end_xfer & ISP1362_avalon_slave_0_allgrants) | (ISP1362_avalon_slave_0_end_xfer & ~ISP1362_avalon_slave_0_non_bursting_master_requests);
//ISP1362_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalon_slave_0_arb_share_counter <= 0;
else if (ISP1362_avalon_slave_0_arb_counter_enable)
ISP1362_avalon_slave_0_arb_share_counter <= ISP1362_avalon_slave_0_arb_share_counter_next_value;
end
//ISP1362_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|ISP1362_avalon_slave_0_master_qreq_vector & ISP1362_avalon_slave_0_end_xfer) | (ISP1362_avalon_slave_0_end_xfer & ~ISP1362_avalon_slave_0_non_bursting_master_requests))
ISP1362_avalon_slave_0_slavearbiterlockenable <= |ISP1362_avalon_slave_0_arb_share_counter_next_value;
end
//cpu_0/data_master ISP1362/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = ISP1362_avalon_slave_0_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//ISP1362_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign ISP1362_avalon_slave_0_slavearbiterlockenable2 = |ISP1362_avalon_slave_0_arb_share_counter_next_value;
//cpu_0/data_master ISP1362/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = ISP1362_avalon_slave_0_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//ISP1362_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
assign ISP1362_avalon_slave_0_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_ISP1362_avalon_slave_0 = cpu_0_data_master_requests_ISP1362_avalon_slave_0;
//ISP1362_avalon_slave_0_writedata mux, which is an e_mux
assign ISP1362_avalon_slave_0_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_ISP1362_avalon_slave_0 = cpu_0_data_master_qualified_request_ISP1362_avalon_slave_0;
//cpu_0/data_master saved-grant ISP1362/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_saved_grant_ISP1362_avalon_slave_0 = cpu_0_data_master_requests_ISP1362_avalon_slave_0;
//allow new arb cycle for ISP1362/avalon_slave_0, which is an e_assign
assign ISP1362_avalon_slave_0_allow_new_arb_cycle = 1;
//placeholder chosen master
assign ISP1362_avalon_slave_0_grant_vector = 1;
//placeholder vector of master qualified-requests
assign ISP1362_avalon_slave_0_master_qreq_vector = 1;
//ISP1362_avalon_slave_0_reset_n assignment, which is an e_assign
assign ISP1362_avalon_slave_0_reset_n = reset_n;
assign ISP1362_avalon_slave_0_chipselect_n = ~cpu_0_data_master_granted_ISP1362_avalon_slave_0;
//ISP1362_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign ISP1362_avalon_slave_0_firsttransfer = ~(ISP1362_avalon_slave_0_slavearbiterlockenable & ISP1362_avalon_slave_0_any_continuerequest);
//ISP1362_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign ISP1362_avalon_slave_0_beginbursttransfer_internal = ISP1362_avalon_slave_0_begins_xfer & ISP1362_avalon_slave_0_firsttransfer;
//~ISP1362_avalon_slave_0_read_n assignment, which is an e_mux
assign ISP1362_avalon_slave_0_read_n = ~(((cpu_0_data_master_granted_ISP1362_avalon_slave_0 & cpu_0_data_master_read))& ~ISP1362_avalon_slave_0_begins_xfer & (ISP1362_avalon_slave_0_wait_counter < 10));
//~ISP1362_avalon_slave_0_write_n assignment, which is an e_mux
assign ISP1362_avalon_slave_0_write_n = ~(((cpu_0_data_master_granted_ISP1362_avalon_slave_0 & cpu_0_data_master_write)) & ~ISP1362_avalon_slave_0_begins_xfer & (ISP1362_avalon_slave_0_wait_counter >= 10) & (ISP1362_avalon_slave_0_wait_counter < 20));
//ISP1362_avalon_slave_0_address mux, which is an e_mux
assign ISP1362_avalon_slave_0_address = cpu_0_data_master_address_to_slave >> 2;
//d1_ISP1362_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_ISP1362_avalon_slave_0_end_xfer <= 1;
else if (1)
d1_ISP1362_avalon_slave_0_end_xfer <= ISP1362_avalon_slave_0_end_xfer;
end
//ISP1362_avalon_slave_0_wait_counter_eq_1 assignment, which is an e_assign
assign ISP1362_avalon_slave_0_wait_counter_eq_1 = ISP1362_avalon_slave_0_wait_counter == 1;
//ISP1362_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign ISP1362_avalon_slave_0_waits_for_read = ISP1362_avalon_slave_0_in_a_read_cycle & wait_for_ISP1362_avalon_slave_0_counter;
//ISP1362_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign ISP1362_avalon_slave_0_in_a_read_cycle = cpu_0_data_master_granted_ISP1362_avalon_slave_0 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = ISP1362_avalon_slave_0_in_a_read_cycle;
//ISP1362_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign ISP1362_avalon_slave_0_waits_for_write = ISP1362_avalon_slave_0_in_a_write_cycle & wait_for_ISP1362_avalon_slave_0_counter;
//ISP1362_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign ISP1362_avalon_slave_0_in_a_write_cycle = cpu_0_data_master_granted_ISP1362_avalon_slave_0 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = ISP1362_avalon_slave_0_in_a_write_cycle;
assign ISP1362_avalon_slave_0_wait_counter_eq_0 = ISP1362_avalon_slave_0_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ISP1362_avalon_slave_0_wait_counter <= 0;
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