📄 system_0.v
字号:
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
DM9000A_avalon_slave_0_address,
DM9000A_avalon_slave_0_chipselect_n,
DM9000A_avalon_slave_0_irq_from_sa,
DM9000A_avalon_slave_0_read_n,
DM9000A_avalon_slave_0_readdata_from_sa,
DM9000A_avalon_slave_0_reset_n,
DM9000A_avalon_slave_0_wait_counter_eq_0,
DM9000A_avalon_slave_0_wait_counter_eq_1,
DM9000A_avalon_slave_0_write_n,
DM9000A_avalon_slave_0_writedata,
cpu_0_data_master_granted_DM9000A_avalon_slave_0,
cpu_0_data_master_qualified_request_DM9000A_avalon_slave_0,
cpu_0_data_master_read_data_valid_DM9000A_avalon_slave_0,
cpu_0_data_master_requests_DM9000A_avalon_slave_0,
d1_DM9000A_avalon_slave_0_end_xfer
)
/* synthesis auto_dissolve = "FALSE" */ ;
output DM9000A_avalon_slave_0_address;
output DM9000A_avalon_slave_0_chipselect_n;
output DM9000A_avalon_slave_0_irq_from_sa;
output DM9000A_avalon_slave_0_read_n;
output [ 15: 0] DM9000A_avalon_slave_0_readdata_from_sa;
output DM9000A_avalon_slave_0_reset_n;
output DM9000A_avalon_slave_0_wait_counter_eq_0;
output DM9000A_avalon_slave_0_wait_counter_eq_1;
output DM9000A_avalon_slave_0_write_n;
output [ 15: 0] DM9000A_avalon_slave_0_writedata;
output cpu_0_data_master_granted_DM9000A_avalon_slave_0;
output cpu_0_data_master_qualified_request_DM9000A_avalon_slave_0;
output cpu_0_data_master_read_data_valid_DM9000A_avalon_slave_0;
output cpu_0_data_master_requests_DM9000A_avalon_slave_0;
output d1_DM9000A_avalon_slave_0_end_xfer;
input DM9000A_avalon_slave_0_irq;
input [ 15: 0] DM9000A_avalon_slave_0_readdata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire DM9000A_avalon_slave_0_address;
wire DM9000A_avalon_slave_0_allgrants;
wire DM9000A_avalon_slave_0_allow_new_arb_cycle;
wire DM9000A_avalon_slave_0_any_continuerequest;
wire DM9000A_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] DM9000A_avalon_slave_0_arb_share_counter;
wire [ 2: 0] DM9000A_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] DM9000A_avalon_slave_0_arb_share_set_values;
wire DM9000A_avalon_slave_0_beginbursttransfer_internal;
wire DM9000A_avalon_slave_0_begins_xfer;
wire DM9000A_avalon_slave_0_chipselect_n;
wire [ 1: 0] DM9000A_avalon_slave_0_counter_load_value;
wire DM9000A_avalon_slave_0_end_xfer;
wire DM9000A_avalon_slave_0_firsttransfer;
wire DM9000A_avalon_slave_0_grant_vector;
wire DM9000A_avalon_slave_0_in_a_read_cycle;
wire DM9000A_avalon_slave_0_in_a_write_cycle;
wire DM9000A_avalon_slave_0_irq_from_sa;
wire DM9000A_avalon_slave_0_master_qreq_vector;
wire DM9000A_avalon_slave_0_non_bursting_master_requests;
wire DM9000A_avalon_slave_0_read_n;
wire [ 15: 0] DM9000A_avalon_slave_0_readdata_from_sa;
wire DM9000A_avalon_slave_0_reset_n;
reg DM9000A_avalon_slave_0_slavearbiterlockenable;
wire DM9000A_avalon_slave_0_slavearbiterlockenable2;
reg [ 1: 0] DM9000A_avalon_slave_0_wait_counter;
wire DM9000A_avalon_slave_0_wait_counter_eq_0;
wire DM9000A_avalon_slave_0_wait_counter_eq_1;
wire DM9000A_avalon_slave_0_waits_for_read;
wire DM9000A_avalon_slave_0_waits_for_write;
wire DM9000A_avalon_slave_0_write_n;
wire [ 15: 0] DM9000A_avalon_slave_0_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_DM9000A_avalon_slave_0;
wire cpu_0_data_master_qualified_request_DM9000A_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_DM9000A_avalon_slave_0;
wire cpu_0_data_master_requests_DM9000A_avalon_slave_0;
wire cpu_0_data_master_saved_grant_DM9000A_avalon_slave_0;
reg d1_DM9000A_avalon_slave_0_end_xfer;
reg d1_reasons_to_wait;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire wait_for_DM9000A_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else if (1)
d1_reasons_to_wait <= ~DM9000A_avalon_slave_0_end_xfer;
end
assign DM9000A_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_DM9000A_avalon_slave_0));
//assign DM9000A_avalon_slave_0_readdata_from_sa = DM9000A_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign DM9000A_avalon_slave_0_readdata_from_sa = DM9000A_avalon_slave_0_readdata;
assign cpu_0_data_master_requests_DM9000A_avalon_slave_0 = ({cpu_0_data_master_address_to_slave[23 : 3] , 3'b0} == 24'h6810f8) & (cpu_0_data_master_read | cpu_0_data_master_write);
//DM9000A_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign DM9000A_avalon_slave_0_arb_share_set_values = 1;
//DM9000A_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign DM9000A_avalon_slave_0_non_bursting_master_requests = cpu_0_data_master_requests_DM9000A_avalon_slave_0;
//DM9000A_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign DM9000A_avalon_slave_0_arb_share_counter_next_value = DM9000A_avalon_slave_0_firsttransfer ? (DM9000A_avalon_slave_0_arb_share_set_values - 1) : |DM9000A_avalon_slave_0_arb_share_counter ? (DM9000A_avalon_slave_0_arb_share_counter - 1) : 0;
//DM9000A_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign DM9000A_avalon_slave_0_allgrants = |DM9000A_avalon_slave_0_grant_vector;
//DM9000A_avalon_slave_0_end_xfer assignment, which is an e_assign
assign DM9000A_avalon_slave_0_end_xfer = ~(DM9000A_avalon_slave_0_waits_for_read | DM9000A_avalon_slave_0_waits_for_write);
//DM9000A_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign DM9000A_avalon_slave_0_arb_counter_enable = (DM9000A_avalon_slave_0_end_xfer & DM9000A_avalon_slave_0_allgrants) | (DM9000A_avalon_slave_0_end_xfer & ~DM9000A_avalon_slave_0_non_bursting_master_requests);
//DM9000A_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalon_slave_0_arb_share_counter <= 0;
else if (DM9000A_avalon_slave_0_arb_counter_enable)
DM9000A_avalon_slave_0_arb_share_counter <= DM9000A_avalon_slave_0_arb_share_counter_next_value;
end
//DM9000A_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|DM9000A_avalon_slave_0_master_qreq_vector & DM9000A_avalon_slave_0_end_xfer) | (DM9000A_avalon_slave_0_end_xfer & ~DM9000A_avalon_slave_0_non_bursting_master_requests))
DM9000A_avalon_slave_0_slavearbiterlockenable <= |DM9000A_avalon_slave_0_arb_share_counter_next_value;
end
//cpu_0/data_master DM9000A/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = DM9000A_avalon_slave_0_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//DM9000A_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign DM9000A_avalon_slave_0_slavearbiterlockenable2 = |DM9000A_avalon_slave_0_arb_share_counter_next_value;
//cpu_0/data_master DM9000A/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = DM9000A_avalon_slave_0_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//DM9000A_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
assign DM9000A_avalon_slave_0_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_DM9000A_avalon_slave_0 = cpu_0_data_master_requests_DM9000A_avalon_slave_0;
//DM9000A_avalon_slave_0_writedata mux, which is an e_mux
assign DM9000A_avalon_slave_0_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_DM9000A_avalon_slave_0 = cpu_0_data_master_qualified_request_DM9000A_avalon_slave_0;
//cpu_0/data_master saved-grant DM9000A/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_saved_grant_DM9000A_avalon_slave_0 = cpu_0_data_master_requests_DM9000A_avalon_slave_0;
//allow new arb cycle for DM9000A/avalon_slave_0, which is an e_assign
assign DM9000A_avalon_slave_0_allow_new_arb_cycle = 1;
//placeholder chosen master
assign DM9000A_avalon_slave_0_grant_vector = 1;
//placeholder vector of master qualified-requests
assign DM9000A_avalon_slave_0_master_qreq_vector = 1;
//DM9000A_avalon_slave_0_reset_n assignment, which is an e_assign
assign DM9000A_avalon_slave_0_reset_n = reset_n;
assign DM9000A_avalon_slave_0_chipselect_n = ~cpu_0_data_master_granted_DM9000A_avalon_slave_0;
//DM9000A_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign DM9000A_avalon_slave_0_firsttransfer = ~(DM9000A_avalon_slave_0_slavearbiterlockenable & DM9000A_avalon_slave_0_any_continuerequest);
//DM9000A_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign DM9000A_avalon_slave_0_beginbursttransfer_internal = DM9000A_avalon_slave_0_begins_xfer & DM9000A_avalon_slave_0_firsttransfer;
//~DM9000A_avalon_slave_0_read_n assignment, which is an e_mux
assign DM9000A_avalon_slave_0_read_n = ~(cpu_0_data_master_granted_DM9000A_avalon_slave_0 & cpu_0_data_master_read);
//~DM9000A_avalon_slave_0_write_n assignment, which is an e_mux
assign DM9000A_avalon_slave_0_write_n = ~(cpu_0_data_master_granted_DM9000A_avalon_slave_0 & cpu_0_data_master_write);
//DM9000A_avalon_slave_0_address mux, which is an e_mux
assign DM9000A_avalon_slave_0_address = cpu_0_data_master_address_to_slave >> 2;
//d1_DM9000A_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_DM9000A_avalon_slave_0_end_xfer <= 1;
else if (1)
d1_DM9000A_avalon_slave_0_end_xfer <= DM9000A_avalon_slave_0_end_xfer;
end
//DM9000A_avalon_slave_0_wait_counter_eq_1 assignment, which is an e_assign
assign DM9000A_avalon_slave_0_wait_counter_eq_1 = DM9000A_avalon_slave_0_wait_counter == 1;
//DM9000A_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign DM9000A_avalon_slave_0_waits_for_read = DM9000A_avalon_slave_0_in_a_read_cycle & wait_for_DM9000A_avalon_slave_0_counter;
//DM9000A_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign DM9000A_avalon_slave_0_in_a_read_cycle = cpu_0_data_master_granted_DM9000A_avalon_slave_0 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = DM9000A_avalon_slave_0_in_a_read_cycle;
//DM9000A_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign DM9000A_avalon_slave_0_waits_for_write = DM9000A_avalon_slave_0_in_a_write_cycle & wait_for_DM9000A_avalon_slave_0_counter;
//DM9000A_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign DM9000A_avalon_slave_0_in_a_write_cycle = cpu_0_data_master_granted_DM9000A_avalon_slave_0 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = DM9000A_avalon_slave_0_in_a_write_cycle;
assign DM9000A_avalon_slave_0_wait_counter_eq_0 = DM9000A_avalon_slave_0_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
DM9000A_avalon_slave_0_wait_counter <= 0;
else if (1)
DM9000A_avalon_slave_0_wait_counter <= DM9000A_avalon_slave_0_counter_load_value;
end
assign DM9000A_avalon_slave_0_counter_load_value = ((DM9000A_avalon_slave_0_in_a_write_cycle & DM9000A_avalon_slave_0_begins_xfer))? 2 :
((DM9000A_avalon_slave_0_in_a_read_cycle & DM9000A_avalon_slave_0_begins_xfer))? 2 :
(~DM9000A_avalon_slave_0_wait_counter_eq_0)? DM9000A_avalon_slave_0_wait_counter - 1 :
0;
assign wait_for_DM9000A_avalon_slave_0_counter = DM9000A_avalon_slave_0_begins_xfer | ~DM9000A_avalon_slave_0_wait_counter_eq_0;
//assign DM9000A_avalon_slave_0_irq_from_sa = DM9000A_avalon_slave_0_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign DM9000A_avalon_slave_0_irq_from_sa = DM9000A_avalon_slave_0_irq;
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