📄 system_0.v
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//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
//Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Audio_0_avalon_slave_0_arbitrator (
// inputs:
Audio_0_avalon_slave_0_readdata,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
Audio_0_avalon_slave_0_readdata_from_sa,
Audio_0_avalon_slave_0_reset_n,
Audio_0_avalon_slave_0_write,
Audio_0_avalon_slave_0_writedata,
cpu_0_data_master_granted_Audio_0_avalon_slave_0,
cpu_0_data_master_qualified_request_Audio_0_avalon_slave_0,
cpu_0_data_master_read_data_valid_Audio_0_avalon_slave_0,
cpu_0_data_master_requests_Audio_0_avalon_slave_0,
d1_Audio_0_avalon_slave_0_end_xfer
)
/* synthesis auto_dissolve = "FALSE" */ ;
output [ 15: 0] Audio_0_avalon_slave_0_readdata_from_sa;
output Audio_0_avalon_slave_0_reset_n;
output Audio_0_avalon_slave_0_write;
output [ 15: 0] Audio_0_avalon_slave_0_writedata;
output cpu_0_data_master_granted_Audio_0_avalon_slave_0;
output cpu_0_data_master_qualified_request_Audio_0_avalon_slave_0;
output cpu_0_data_master_read_data_valid_Audio_0_avalon_slave_0;
output cpu_0_data_master_requests_Audio_0_avalon_slave_0;
output d1_Audio_0_avalon_slave_0_end_xfer;
input [ 15: 0] Audio_0_avalon_slave_0_readdata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire Audio_0_avalon_slave_0_address_for_slave_wo_address;
wire Audio_0_avalon_slave_0_allgrants;
wire Audio_0_avalon_slave_0_allow_new_arb_cycle;
wire Audio_0_avalon_slave_0_any_continuerequest;
wire Audio_0_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] Audio_0_avalon_slave_0_arb_share_counter;
wire [ 2: 0] Audio_0_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] Audio_0_avalon_slave_0_arb_share_set_values;
wire Audio_0_avalon_slave_0_beginbursttransfer_internal;
wire Audio_0_avalon_slave_0_begins_xfer;
wire Audio_0_avalon_slave_0_end_xfer;
wire Audio_0_avalon_slave_0_firsttransfer;
wire Audio_0_avalon_slave_0_grant_vector;
wire Audio_0_avalon_slave_0_in_a_read_cycle;
wire Audio_0_avalon_slave_0_in_a_write_cycle;
wire Audio_0_avalon_slave_0_master_qreq_vector;
wire Audio_0_avalon_slave_0_non_bursting_master_requests;
wire [ 15: 0] Audio_0_avalon_slave_0_readdata_from_sa;
wire Audio_0_avalon_slave_0_reset_n;
reg Audio_0_avalon_slave_0_slavearbiterlockenable;
wire Audio_0_avalon_slave_0_slavearbiterlockenable2;
wire Audio_0_avalon_slave_0_waits_for_read;
wire Audio_0_avalon_slave_0_waits_for_write;
wire Audio_0_avalon_slave_0_write;
wire [ 15: 0] Audio_0_avalon_slave_0_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_Audio_0_avalon_slave_0;
wire cpu_0_data_master_qualified_request_Audio_0_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_Audio_0_avalon_slave_0;
wire cpu_0_data_master_requests_Audio_0_avalon_slave_0;
wire cpu_0_data_master_saved_grant_Audio_0_avalon_slave_0;
reg d1_Audio_0_avalon_slave_0_end_xfer;
reg d1_reasons_to_wait;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire wait_for_Audio_0_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else if (1)
d1_reasons_to_wait <= ~Audio_0_avalon_slave_0_end_xfer;
end
assign Audio_0_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Audio_0_avalon_slave_0));
//assign Audio_0_avalon_slave_0_readdata_from_sa = Audio_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign Audio_0_avalon_slave_0_readdata_from_sa = Audio_0_avalon_slave_0_readdata;
assign cpu_0_data_master_requests_Audio_0_avalon_slave_0 = ({cpu_0_data_master_address_to_slave[23 : 2] , 2'b0} == 24'h681104) & (cpu_0_data_master_read | cpu_0_data_master_write);
//Audio_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign Audio_0_avalon_slave_0_arb_share_set_values = 1;
//Audio_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign Audio_0_avalon_slave_0_non_bursting_master_requests = cpu_0_data_master_requests_Audio_0_avalon_slave_0;
//Audio_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign Audio_0_avalon_slave_0_arb_share_counter_next_value = Audio_0_avalon_slave_0_firsttransfer ? (Audio_0_avalon_slave_0_arb_share_set_values - 1) : |Audio_0_avalon_slave_0_arb_share_counter ? (Audio_0_avalon_slave_0_arb_share_counter - 1) : 0;
//Audio_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign Audio_0_avalon_slave_0_allgrants = |Audio_0_avalon_slave_0_grant_vector;
//Audio_0_avalon_slave_0_end_xfer assignment, which is an e_assign
assign Audio_0_avalon_slave_0_end_xfer = ~(Audio_0_avalon_slave_0_waits_for_read | Audio_0_avalon_slave_0_waits_for_write);
//Audio_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign Audio_0_avalon_slave_0_arb_counter_enable = (Audio_0_avalon_slave_0_end_xfer & Audio_0_avalon_slave_0_allgrants) | (Audio_0_avalon_slave_0_end_xfer & ~Audio_0_avalon_slave_0_non_bursting_master_requests);
//Audio_0_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Audio_0_avalon_slave_0_arb_share_counter <= 0;
else if (Audio_0_avalon_slave_0_arb_counter_enable)
Audio_0_avalon_slave_0_arb_share_counter <= Audio_0_avalon_slave_0_arb_share_counter_next_value;
end
//Audio_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Audio_0_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|Audio_0_avalon_slave_0_master_qreq_vector & Audio_0_avalon_slave_0_end_xfer) | (Audio_0_avalon_slave_0_end_xfer & ~Audio_0_avalon_slave_0_non_bursting_master_requests))
Audio_0_avalon_slave_0_slavearbiterlockenable <= |Audio_0_avalon_slave_0_arb_share_counter_next_value;
end
//cpu_0/data_master Audio_0/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = Audio_0_avalon_slave_0_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//Audio_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign Audio_0_avalon_slave_0_slavearbiterlockenable2 = |Audio_0_avalon_slave_0_arb_share_counter_next_value;
//cpu_0/data_master Audio_0/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = Audio_0_avalon_slave_0_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//Audio_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
assign Audio_0_avalon_slave_0_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_Audio_0_avalon_slave_0 = cpu_0_data_master_requests_Audio_0_avalon_slave_0 & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//Audio_0_avalon_slave_0_writedata mux, which is an e_mux
assign Audio_0_avalon_slave_0_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_Audio_0_avalon_slave_0 = cpu_0_data_master_qualified_request_Audio_0_avalon_slave_0;
//cpu_0/data_master saved-grant Audio_0/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_saved_grant_Audio_0_avalon_slave_0 = cpu_0_data_master_requests_Audio_0_avalon_slave_0;
//allow new arb cycle for Audio_0/avalon_slave_0, which is an e_assign
assign Audio_0_avalon_slave_0_allow_new_arb_cycle = 1;
//placeholder chosen master
assign Audio_0_avalon_slave_0_grant_vector = 1;
//placeholder vector of master qualified-requests
assign Audio_0_avalon_slave_0_master_qreq_vector = 1;
//Audio_0_avalon_slave_0_reset_n assignment, which is an e_assign
assign Audio_0_avalon_slave_0_reset_n = reset_n;
//Audio_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign Audio_0_avalon_slave_0_firsttransfer = ~(Audio_0_avalon_slave_0_slavearbiterlockenable & Audio_0_avalon_slave_0_any_continuerequest);
//Audio_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign Audio_0_avalon_slave_0_beginbursttransfer_internal = Audio_0_avalon_slave_0_begins_xfer & Audio_0_avalon_slave_0_firsttransfer;
//Audio_0_avalon_slave_0_write assignment, which is an e_mux
assign Audio_0_avalon_slave_0_write = cpu_0_data_master_granted_Audio_0_avalon_slave_0 & cpu_0_data_master_write;
//Audio_0_avalon_slave_0_address_for_slave_wo_address mux, which is an e_mux
assign Audio_0_avalon_slave_0_address_for_slave_wo_address = cpu_0_data_master_address_to_slave >> 2;
//d1_Audio_0_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_Audio_0_avalon_slave_0_end_xfer <= 1;
else if (1)
d1_Audio_0_avalon_slave_0_end_xfer <= Audio_0_avalon_slave_0_end_xfer;
end
//Audio_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign Audio_0_avalon_slave_0_waits_for_read = Audio_0_avalon_slave_0_in_a_read_cycle & 0;
//Audio_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign Audio_0_avalon_slave_0_in_a_read_cycle = cpu_0_data_master_granted_Audio_0_avalon_slave_0 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = Audio_0_avalon_slave_0_in_a_read_cycle;
//Audio_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign Audio_0_avalon_slave_0_waits_for_write = Audio_0_avalon_slave_0_in_a_write_cycle & 0;
//Audio_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign Audio_0_avalon_slave_0_in_a_write_cycle = cpu_0_data_master_granted_Audio_0_avalon_slave_0 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = Audio_0_avalon_slave_0_in_a_write_cycle;
assign wait_for_Audio_0_avalon_slave_0_counter = 0;
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DM9000A_avalon_slave_0_arbitrator (
// inputs:
DM9000A_avalon_slave_0_irq,
DM9000A_avalon_slave_0_readdata,
clk,
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