de2_board.flow.rpt

DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等

Flow report for DE2_Board
Thu Nov 17 16:24:49 2005
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Flow Summary                                                                  ;
+------------------------------------+------------------------------------------+
; Flow Status                        ; Successful - Thu Nov 17 16:24:49 2005    ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name                      ; DE2_Board                                ;
; Top-level Entity Name              ; DE2_Board_top                            ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35F672C6                             ;
; Timing Models                      ; Preliminary                              ;
; Met timing requirements            ; Yes                                      ;
; Total logic elements               ; 1,493 / 33,216 ( 4 % )                   ;
; Total registers                    ; 770                                      ;
; Total pins                         ; 36 / 475 ( 8 % )                         ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 177,152 / 483,840 ( 37 % )               ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 11/17/2005 16:22:57 ;
; Main task         ; Compilation         ;
; Revision Name     ; DE2_Board           ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:52     ;
; Fitter               ; 00:00:42     ;
; Assembler            ; 00:00:08     ;
; Timing Analyzer      ; 00:00:04     ;
; Total                ; 00:01:46     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off DE2_Board -c DE2_Board
quartus_fit --read_settings_files=off --write_settings_files=off DE2_Board -c DE2_Board
quartus_asm --read_settings_files=off --write_settings_files=off DE2_Board -c DE2_Board
quartus_tan --read_settings_files=off --write_settings_files=off DE2_Board -c DE2_Board --timing_analysis_only