📄 de2_board.map.rpt
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; |altsyncram_3pc1:altsyncram2| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2 ;
; |altsyncram_0431:altsyncram3| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3 ;
; |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w| ; 35 (0) ; 29 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w ;
; |scfifo:wfifo| ; 35 (0) ; 29 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
; |scfifo_46p:auto_generated| ; 35 (0) ; 29 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated ;
; |a_dpfifo_bcp:dpfifo| ; 35 (0) ; 29 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo ;
; |a_fefifo_odf:fifo_state| ; 17 (8) ; 11 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state ;
; |cntr_uj7:count_usedw| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|a_fefifo_odf:fifo_state|cntr_uj7:count_usedw ;
; |cntr_gl8:rd_ptr_count| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:rd_ptr_count ;
; |cntr_gl8:wr_ptr| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|cntr_gl8:wr_ptr ;
; |dpram_scp:FIFOram| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram ;
; |altsyncram_3pc1:altsyncram2| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2 ;
; |altsyncram_0431:altsyncram3| ; 0 (0) ; 0 (0) ; 4096 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3 ;
; |jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave ;
; |payload_buffer:the_payload_buffer| ; 18 (0) ; 1 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer ;
; |altsyncram:the_altsyncram| ; 18 (0) ; 1 (0) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram ;
; |altsyncram_l331:auto_generated| ; 18 (0) ; 1 (1) ; 131072 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated ;
; |decode_1oa:decode3| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|decode_1oa:decode3 ;
; |mux_0kb:mux2| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|mux_0kb:mux2 ;
; |payload_buffer_s1_arbitrator:the_payload_buffer_s1| ; 49 (49) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1 ;
; |sysid_control_slave_arbitrator:the_sysid_control_slave| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|sysid_control_slave_arbitrator:the_sysid_control_slave ;
; |tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave| ; 75 (75) ; 61 (61) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ;
; |delay_reset_block:inst3| ; 12 (1) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|delay_reset_block:inst3 ;
; |reset_counter:inst| ; 11 (0) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|delay_reset_block:inst3|reset_counter:inst ;
; |lpm_counter:lpm_counter_component| ; 11 (0) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component ;
; |cntr_8bc:auto_generated| ; 11 (11) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated ;
; |sld_hub:sld_hub_inst| ; 76 (26) ; 61 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst ;
; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ;
; |decode_rpe:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_rpe:auto_generated ;
; |lpm_shiftreg:jtag_ir_register| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ;
; |sld_dffex:BROADCAST| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ;
; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ;
; |sld_dffex:IRF_ENA| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ;
; |sld_dffex:IRSR| ; 1 (1) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:IRSR ;
; |sld_dffex:RESET| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:RESET ;
; |sld_dffex:\GEN_IRF:1:IRF| ; 2 (2) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ;
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ;
; |sld_jtag_state_machine:jtag_state_machine| ; 19 (19) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
; |sld_rom_sr:HUB_INFO_REG| ; 19 (19) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DE2_Board_top|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------------+
; DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; rf_ram.mif ;
; DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 256 ; 32 ; -- ; -- ; 8192 ; data_RAM.hex ;
; DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 896 ; 32 ; -- ; -- ; 28672 ; firmware_ROM.hex ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|ALTSYNCRAM ; AUTO ; True Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; None ;
; DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3|ALTSYNCRAM ; AUTO ; True Dual Port ; 512 ; 8 ; 512 ; 8 ; 4096 ; None ;
; DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated|ALTSYNCRAM ; M4K ; Single Port ; 8192 ; 16 ; -- ; -- ; 131072 ; payload_buffer.hex ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by SYN_PRESERVE, DONT_TOUCH ;
+----------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
; Register Name ; Protected by SYN_PRESERVE ; Not to be Touched by Netlist Optimizations ;
+----------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
; DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_out ; yes ; yes ;
; DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_in_d1 ; yes ; yes ;
+----------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------+
+-------------------------------------⌨️ 快捷键说明
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