de2_board.map.rpt

DE2开发板上的资料,主要是他的例子,含有各种接口程序,如VGA,USB,LCD等

Analysis & Synthesis report for DE2_Board
Thu Nov 17 16:23:50 2005
Version 5.1 Build 176 10/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Protected by SYN_PRESERVE, DONT_TOUCH
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Source assignments for DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram|altsyncram_r0r1:auto_generated
 13. Source assignments for DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram|altsyncram_8c21:auto_generated
 14. Source assignments for DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram|altsyncram_cs21:auto_generated
 15. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2
 16. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3
 17. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2
 18. Source assignments for DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_46p:auto_generated|a_dpfifo_bcp:dpfifo|dpram_scp:FIFOram|altsyncram_3pc1:altsyncram2|altsyncram_0431:altsyncram3
 19. Source assignments for DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_l331:auto_generated
 20. Source assignments for DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
 21. Source assignments for DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch
 22. Parameter Settings for User Entity Instance: DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf
 23. Parameter Settings for User Entity Instance: DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram
 24. Parameter Settings for User Entity Instance: DE2_Board:inst|data_RAM:the_data_RAM|altsyncram:the_altsyncram
 25. Parameter Settings for User Entity Instance: DE2_Board:inst|firmware_ROM:the_firmware_ROM|altsyncram:the_altsyncram
 26. Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
 27. Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
 28. Parameter Settings for User Entity Instance: DE2_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
 29. Parameter Settings for User Entity Instance: DE2_Board:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram
 30. Parameter Settings for User Entity Instance: delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
 31. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 32. scfifo Parameter Settings by Entity Instance
 33. Analysis & Synthesis Equations
 34. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



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; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Nov 17 16:23:49 2005    ;
; Quartus II Version                 ; 5.1 Build 176 10/26/2005 SJ Full Version ;