📄 rccu.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.30A/W32 08/Nov/2005 12:06:35 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = D:\Book-IAR\examples_ST\STR71x_ADC\source\rccu.c #
# Command line = D:\Book-IAR\examples_ST\STR71x_ADC\source\rccu.c #
# -lC D:\Book-IAR\examples_ST\STR71x_ADC\Debug\List\ #
# -o D:\Book-IAR\examples_ST\STR71x_ADC\Debug\Obj\ #
# -s2 --no_cse --no_unroll --no_inline #
# --no_code_motion --no_tbaa --no_clustering #
# --no_scheduling --debug --cpu_mode arm --endian #
# little --cpu ARM7TDMI --stack_align 4 --interwork #
# -e --fpu None --dlib_config "d:\IAR #
# Systems\Embedded Workbench #
# 4.0\arm\LIB\dl4tpainl8n.h" -I #
# D:\Book-IAR\examples_ST\STR71x_ADC\ -I #
# D:\Book-IAR\examples_ST\STR71x_ADC\include\ -I #
# D:\Book-IAR\examples_ST\STR71x_ADC\source\ -I #
# "d:\IAR Systems\Embedded Workbench 4.0\arm\INC\" #
# List file = D:\Book-IAR\examples_ST\STR71x_ADC\Debug\List\rccu.l #
# st #
# Object file = D:\Book-IAR\examples_ST\STR71x_ADC\Debug\Obj\rccu.r7 #
# 9 #
# #
# #
##############################################################################
D:\Book-IAR\examples_ST\STR71x_ADC\source\rccu.c
1 // rccu.c
2
3 #include "rccu.h"
\ In segment CODE, align 4, keep-with-next
\ __??Code32?? __code __interwork __atpcs FlagStatus RCCU_Div2Status(void)
\ RCCU_Div2Status:
\ 00000000 1C009FE5 LDR R0,??RCCU_Div2Status_0 ;; RCCU
\ 00000004 000090E5 LDR R0,[R0, #+0]
\ 00000008 080090E5 LDR R0,[R0, #+0x8]
\ 0000000C 800C10E3 TST R0,#+0x8000
\ 00000010 0100000A BEQ ??RCCU_Div2Status_1
\ 00000014 0100A0E3 MOV R0,#+0x1
\ 00000018 000000EA B ??RCCU_Div2Status_2
\ ??RCCU_Div2Status_1:
\ 0000001C 0000A0E3 MOV R0,#+0
\ ??RCCU_Div2Status_2:
\ 00000020 1EFF2FE1 BX LR ;; return
\ ??RCCU_Div2Status_0:
\ 00000024 ........ DC32 RCCU
4
5 /*******************************************************************************
6 * 说明：RCCU_PLL1Config函数，配置PLL1乘、除因子
7 * 参数：New_Mul为乘法因子( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,
8 * RCCU_PLL1_Mul_24 )
9 * New_Div为除法因子 ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
10 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
11 * 返回值：无
12 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
13 void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) {
\ RCCU_PLL1Config:
\ 00000000 04402DE5 STR R4,[SP, #-4]! ;; Push
14 u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
\ 00000004 ........ LDR R3,??DataTable33 ;; RCCU
\ 00000008 003093E5 LDR R3,[R3, #+0]
\ 0000000C 183093E5 LDR R3,[R3, #+0x18]
\ 00000010 3030D3E3 BICS R3,R3,#+0x30
\ 00000014 00C0A0E1 MOV R12,R0
\ 00000018 0C3293E1 ORRS R3,R3,R12, LSL #+0x4
\ 0000001C 0320A0E1 MOV R2,R3
15 RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;
\ 00000020 ........ LDR R3,??DataTable33 ;; RCCU
\ 00000024 003093E5 LDR R3,[R3, #+0]
\ 00000028 A2C1A0E1 MOV R12,R2, LSR #+0x3
\ 0000002C 0140A0E1 MOV R4,R1
\ 00000030 8C4194E1 ORRS R4,R4,R12, LSL #+0x3
\ 00000034 404094E3 ORRS R4,R4,#+0x40
\ 00000038 184083E5 STR R4,[R3, #+0x18]
16 }
\ 0000003C ........ LDR R4,[SP], #+0x4 ;; Pop
\ 00000040 1EFF2FE1 BX LR ;; return
17
18 /*******************************************************************************
19 * 说明：RCCU_PLL2Config函数，配置PLL2乘、除因子
20 * 参数：New_Mul为乘法因子( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,
21 * RCCU_PLL1_Mul_24 )
22 * New_Div为除法因子 ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
23 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)
24 * 返回值：无
25 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
26 void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) {
\ RCCU_PLL2Config:
\ 00000000 04402DE5 STR R4,[SP, #-4]! ;; Push
27 u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );
\ 00000004 ........ LDR R3,??DataTable36 ;; PCU
\ 00000008 003093E5 LDR R3,[R3, #+0]
\ 0000000C BC30D3E1 LDRH R3,[R3, #+0xC]
\ 00000010 3030D3E3 BICS R3,R3,#+0x30
\ 00000014 00C0A0E1 MOV R12,R0
\ 00000018 0C3293E1 ORRS R3,R3,R12, LSL #+0x4
\ 0000001C 0320A0E1 MOV R2,R3
28 PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask );
\ 00000020 ........ LDR R3,??DataTable36 ;; PCU
\ 00000024 003093E5 LDR R3,[R3, #+0]
\ 00000028 02C0A0E1 MOV R12,R2
\ 0000002C F840A0E3 MOV R4,#+0xF8
\ 00000030 FF4C84E3 ORR R4,R4,#+0xFF00
\ 00000034 0C4014E0 ANDS R4,R4,R12
\ 00000038 01C0A0E1 MOV R12,R1
\ 0000003C 80C09CE3 ORRS R12,R12,#+0x80
\ 00000040 04409CE1 ORRS R4,R12,R4
\ 00000044 BC40C3E1 STRH R4,[R3, #+0xC]
29 }
\ 00000048 ........ LDR R4,[SP], #+0x4 ;; Pop
\ 0000004C 1EFF2FE1 BX LR ;; return
30
31 /*******************************************************************************
32 * 说明：RCCU_RCLKSourceConfig函数，选择RCLK源时钟
33 * 参数：New_Clock为新选时钟 ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 )
34 * 返回值：无
35 *******************************************************************************/
\ In segment CODE, align 4, keep-with-next
36 void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) {
37 switch ( New_Clock ) {
\ RCCU_RCLKSourceConfig:
\ 00000000 0010A0E1 MOV R1,R0
\ 00000004 000051E3 CMP R1,#+0
\ 00000008 3B00000A BEQ ??RCCU_RCLKSourceConfig_0
\ 0000000C 010051E3 CMP R1,#+0x1
\ 00000010 2200000A BEQ ??RCCU_RCLKSourceConfig_1
\ 00000014 020051E3 CMP R1,#+0x2
\ 00000018 0200000A BEQ ??RCCU_RCLKSourceConfig_2
\ 0000001C 030051E3 CMP R1,#+0x3
\ 00000020 5600000A BEQ ??RCCU_RCLKSourceConfig_3
\ 00000024 5C0000EA B ??RCCU_RCLKSourceConfig_4
38 case RCCU_CLOCK2 :{// 复位 CSU_Cksel 位
39 RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;
\ ??RCCU_RCLKSourceConfig_2:
\ 00000028 ........ LDR R1,??DataTable33 ;; RCCU
\ 0000002C 001091E5 LDR R1,[R1, #+0]
\ 00000030 ........ LDR R2,??DataTable33 ;; RCCU
\ 00000034 002092E5 LDR R2,[R2, #+0]
\ 00000038 082092E5 LDR R2,[R2, #+0x8]
\ 0000003C 0120D2E3 BICS R2,R2,#+0x1
\ 00000040 082081E5 STR R2,[R1, #+0x8]
40 // 置位 CK2_16 位
41 RCCU->CFR |= RCCU_CK2_16_Mask;
\ 00000044 ........ LDR R1,??DataTable33 ;; RCCU
\ 00000048 001091E5 LDR R1,[R1, #+0]
\ 0000004C ........ LDR R2,??DataTable33 ;; RCCU
\ 00000050 002092E5 LDR R2,[R2, #+0]
\ 00000054 082092E5 LDR R2,[R2, #+0x8]
\ 00000058 082092E3 ORRS R2,R2,#+0x8
\ 0000005C 082081E5 STR R2,[R1, #+0x8]
42 // 反选 CKAF
43 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
\ 00000060 ........ LDR R1,??DataTable33 ;; RCCU
\ 00000064 001091E5 LDR R1,[R1, #+0]
\ 00000068 ........ LDR R2,??DataTable33 ;; RCCU
\ 0000006C 002092E5 LDR R2,[R2, #+0]
\ 00000070 002092E5 LDR R2,[R2, #+0]
\ 00000074 0420D2E3 BICS R2,R2,#+0x4
\ 00000078 002081E5 STR R2,[R1, #+0]
44 // 关闭 PLL1
45 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\
46 |0x00000003) & ~RCCU_FREEN_Mask;
\ 0000007C ........ LDR R1,??DataTable33 ;; RCCU
\ 00000080 001091E5 LDR R1,[R1, #+0]
\ 00000084 ........ LDR R2,??DataTable33 ;; RCCU
\ 00000088 002092E5 LDR R2,[R2, #+0]
\ 0000008C 182092E5 LDR R2,[R2, #+0x18]
\ 00000090 8720D2E3 BICS R2,R2,#+0x87
\ 00000094 032092E3 ORRS R2,R2,#+0x3
\ 00000098 182081E5 STR R2,[R1, #+0x18]
47 break;}
\ 0000009C 3E0000EA B ??RCCU_RCLKSourceConfig_4
48 case RCCU_CLOCK2_16 :{// 复位 CK2_16 位
49 RCCU->CFR &= ~RCCU_CK2_16_Mask;
\ ??RCCU_RCLKSourceConfig_1:
\ 000000A0 ........ LDR R1,??DataTable33 ;; RCCU
\ 000000A4 001091E5 LDR R1,[R1, #+0]
\ 000000A8 ........ LDR R2,??DataTable33 ;; RCCU
\ 000000AC 002092E5 LDR R2,[R2, #+0]
\ 000000B0 082092E5 LDR R2,[R2, #+0x8]
\ 000000B4 0820D2E3 BICS R2,R2,#+0x8
\ 000000B8 082081E5 STR R2,[R1, #+0x8]
50 // 反选 CKAF
51 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
\ 000000BC ........ LDR R1,??DataTable33 ;; RCCU
\ 000000C0 001091E5 LDR R1,[R1, #+0]
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