uart.vhd

Universal async Transmitter Receiver

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PISO is
Port ( 
	data : in std_logic_vector(7 downto 0);
	sout : out std_logic;
	clk	 : in std_logic;
	wr 	 : in std_logic;
	txrdy: out STD_LOGIC;
	reset: in std_logic
	);
end PISO;
architecture Behavioral of PISO is
signal thr:std_logic_vector(7 downto 0):="00000000";
signal tsr:std_logic_vector(7 downto 0):="00000000";
signal txclk : STD_LOGIC;-- Transmit clock, i.e. baudrate clock 
--signal txdone : STD_LOGIC;-- Set to high, when shifting of byte is done
--signal txdatardy : STD_LOGIC; -- Set to high, when data is ready in transmit hold register
signal cnt : STD_LOGIC_VECTOR(1 downto 0); -- Counter used for generating the internal baud rate clock


begin

process (clk, reset)
begin
	if (reset) = '1'  then
		txclk <= '0';
		cnt <= (others => '0');
	elsif (clk'event and clk = '1' ) then
		if cnt >= "1" then	  
			txclk <= not(txclk);
			cnt <= (others => '0');
		else
			cnt <= cnt + '1';
		end if ;
	end if ;
end process ;


process(data,txclk,wr)
begin
--	if (reset) = '1' then 
--		tsr <= "00000000";
--		sout <= '1';
--	elsif txclk'event and txclk ='1' then
	if txclk'event and txclk ='1' then
		if wr = '1' then
			tsr <= data;
		else
			sout <= tsr(0);
			tsr(0) <= tsr(1);
			tsr(1) <= tsr(2);
			tsr(2) <= tsr(3);
			tsr(3) <= tsr(4);
			tsr(4) <= tsr(5);
			tsr(5) <= tsr(6);
			tsr(6) <= tsr(7);
			tsr(7) <= '0';
		end if;
	end if;
end process;
end Behavioral;